ST7LITE20 datasheet(27/131 Pages) STMICROELECTRONICS

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7.5 RESET SEQUENCE MANAGER (RSM)

7.5.1 Introduction

The reset sequence manager includes three RE-

SET sources as shown in Figure 15:

External RESET source pulse

Internal LVD RESET (Low Voltage Detection)

Internal WATCHDOG RESET

These sources act on the RESET pin and it is al-

ways kept low during the delay phase.

The RESET service routine vector is fixed at ad-

dresses FFFEh-FFFFh in the ST7 memory map.

The basic RESET sequence consists of 3 phases

as shown in Figure 14:

Active Phase depending on the RESET source

256 or 4096 CPU clock cycle delay (see table

below)

RESET vector fetch

The 256 or 4096 CPU clock cycle delay allows the

oscillator to stabilise and ensures that recovery

has taken place from the Reset state. The shorter

or longer clock cycle delay is automatically select-

ed depending on the clock source chosen by op-

tion byte:

The RESET vector fetch phase duration is 2 clock

cycles.

If the PLL is enabled by option byte, it outputs the

clock after an additional delay of tSTARTUP (see

Figure 12).

Figure 14. RESET Sequence Phases

7.5.2 Asynchronous External RESET pin

The RESET pin is both an input and an open-drain

output with integrated RON weak pull-up resistor.

This pull-up has no fixed value but varies in ac-

cordance with the input voltage. It can be pulled

low by external circuitry to reset the device. See

Electrical Characteristic section for more details.

A RESET signal originating from an external

source must have a duration of at least th(RSTL)in in

order to be recognized (see Figure 16). This de-

tection is asynchronous and therefore the MCU

can enter reset state even in HALT mode.

Figure 15. Reset Block Diagram

Clock Source

CPU clock

cycle delay

Internal RC Oscillator

256

External clock (connected to CLKIN pin)

256

External Crystal/Ceramic Oscillator

(connected to OSC1/OSC2 pins)

4096

RESET

Active Phase

INTERNAL RESET

256 or 4096 CLOCK CYCLES

FETCH

VECTOR

RESET

RON

VDD

WATCHDOG RESET

LVD RESET

INTERNAL

RESET

PULSE

GENERATOR

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