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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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ST7SCR 数据表(PDF) 79 Page - STMicroelectronics |
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ST7SCR 数据表(HTML) 79 Page - STMicroelectronics |
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79 / 102 page  ST7SCR 79/102 14.3 SUPPLY AND RESET CHARACTERISTICS (T = 0 to +70oC, VDD - VSS = 5.5V unless otherwise specified. 14.4 CLOCK AND TIMING CHARACTERISTICS 14.4.1 General Timings (Operating conditions T A = 0 to +70°C unless otherwise specified) * ∆t INST is the number of tCPU to finish the current instruction execution. 14.4.2 External Clock Source LOW VOLTAGE DETECTOR AND SUPERVISOR (LVDS) Symbol Parameter Conditions Min Typ Max Unit VIT+ Reset release threshold (VDD rising) 3.7 3.9 V VIT- Reset generation threshold (VDD falling) 3.3 3.5 V Vhys Hysteresis VIT+ - VIT- 200 mV VtPOR VDD rise time rate 20 ms/V Symbol Parameter Conditions Min Typ 1) Max Unit tc(INST) Instruction cycle time 2 3 12 tCPU fCPU=4MHz 500 750 3000 ns tv(IT) Interrupt reaction time 2) tv(IT) = ∆tc(INST) + 10 10 22 tCPU fCPU=4MHz 2.5 5.5 µs Symbol Parameter Conditions Min Typ Max Unit VOSC1H OSC1 input pin high level voltage see Figure 38 0.7xVDD VDD V VOSC1L OSC1 input pin low level voltage VSS 0.3xVDD tw(OSC1H) tw(OSC1L) OSC1 high or low time 3) 15 ns tr(OSC1) tf(OSC1) OSC1 rise or fall time 3) 15 IL OSCx Input leakage current VSS≤VIN≤VDD ±1 µA |
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