ST7SCR1R4T1 datasheet(99/102 Pages) STMICROELECTRONICS

99 / 102 page

Rev. 1.2

March 2003

99/102

ERRATA SHEET

ST7SCR LIMITATIONS AND CORRECTIONS

18 SILICON IDENTIFICATION

This document refers only to ST7FSCR devices shown in Table 25. They are identifiable both

by the last letter of the Trace code marked on the device package and by the last 3 digits of

the Internal Sales Type printed on the box label (see also Figure 51)

Table 25. Device Identification

19 REFERENCE SPECIFICATION

ST7SCR Datasheet 1.3 (March 2003).

20 SILICON LIMITATIONS

20.1 UNEXPECTED RESET FETCH

If an interrupt request occurs while a "POP CC" instruction is executed, the interrupt controller

does not recognise the source of the interrupt and, by default, passes the RESET vector ad-

dress to the CPU.

To solve this issue, a "POP CC" instruction must always be preceded by a "SIM" instruction.

20.2 USB: TWO CONSECUTIVE SETUP TOKENS

Description

When two consecutive SETUP tokens are received and the software does not have time to

write the value 8 in the Endpoint 0 Reception Counter Register (CNT0RXR), the data associ-

ated with the second SETUP are not copied to the buffer.

Impact

The impact depends on the host behaviour. In the USB Spec 2.0 it is stated (chapter 5.5.5

p43) that: “A Setup transaction should not normally be sent before the completion of a pre-

vious control transfer. However, if a transfer is aborted, for example, due to errors on the bus,

the host can send the next Setup transaction prematurely from the endpoint’s perspective”. If

the new Setup token is sent because an error occurs in the previous one, it should contain the

same data so no application malfunction will occur.

Trace Code marked on device

Internal Sales Type on box label

Flash Devices:

“xxxxxxxxxX”

7FSCRxxxx$M1

7FSCRxxxx$T1

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