ST92195B datasheet(6/22 Pages) STMICROELECTRONICS

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ST92195B - GENERAL DESCRIPTION

PIN DESCRIPTION (Cont’d)

RESET

Reset (input, active low). The ST9+ is ini-

tialised by the Reset signal. With the deactivation

of RESET, program execution begins from the

Program memory location pointed to by the vector

contained in program memory locations 00h and

01h.

R/G/B

Red/Green/Blue. Video color analog DAC

outputs.

Fast Blanking. Video analog DAC output.

VDD Main power supply voltage (5V±10%, digital)

WSCF, WSCR Analog pins for the VPS/WSS slic-

er . These pins must be tied to ground or not con-

nected.

VPP: On EPROM/OTP devices, the WSCR pin is

replaced by VPP which is the programming voltage

pin. VPP should be tied to GND in user mode.

MCFM Analog pin for the display pixel frequency

multiplier.

OSCIN, OSCOUT

Oscillator (input and output).

These pins connect a parallel-resonant crystal

(24MHz maximum), or an external source to the

on-chip clock oscillator and buffer. OSCIN is the

input of the oscillator inverter and internal clock

generator; OSCOUT is the output of the oscillator

inverter.

VSYNC

Vertical Sync. Vertical video synchronisa-

tion input to OSD. Positive or negative polarity.

HSYNC/CSYNC

Horizontal/Composite sync. Hori-

zontal or composite video synchronisation input to

OSD. Positive or negative polarity.

PXFM Analog pin for the Display Pixel Frequency

Multiplier

AVDD3

Analog VDD of PLL. This pin must be tied

to VDD externally.

GND Digital circuit ground.

AGND Analog circuit ground (must be tied exter-

nally to digital GND).

CVBS1 Composite video input signal for the Tele-

text slicer and sync extraction.

CVBS2 Composite video input signal for the VPS/

WSS slicer. Pin AC coupled.

AVDD1, AVDD2 Analog power supplies (must be

tied externally to AVDD3).

TXCF Analog pin for the Teletext slicer line PLL.

CVBSO, JTDO, JTCK Test pins: leave floating.

TEST0 Test pins: must be tied to AVDD2.

JTRST0 Test pin: must be tied to GND.

Figure 3. 56-Pin Package Pin-Out

INT7/P2.0

RESET

P0.7

P0.6

P0.5

P0.4

P0.3

AIN4/P0.2

P0.1

P0.0

CSO/RE SET0/P3.7

P3.6

P3.5

P3.4

SDI/SDO/ P5.1

SCK/INT2/P5. 0

VDD

JTDO

WSC F

VPP/WSCR

AVDD3

TEST 0

MCFM

JTCK

P2.1/INT5/AIN1

P2.2/INT0/AIN2

P2.3/INT6/VS01

P2.4/NMI

P2.5/AIN3/INT4 /VS02

OSCIN

OSCOUT

P4.7/PWM7/EX TRG/ST OUT

P4.6/PWM6

P4.5/PWM5

P4.4/PWM4

P4.3/PWM3/TSL U/HT

P4.2/PWM2

P4.1/PWM1

P4.0/PWM0

VSYNC

HSYNC/CSYNC

AVDD1

PXFM

JTRSTO

GND

AGND

CVBS 1

CVBS 2

JTMS

AVDD2

CVBS O

TXCF

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