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EM7640FS16AW45LL 数据表(PDF) 5 Page - Emerging Memory & Logic Solutions Inc

部件名 EM7640FS16AW45LL
功能描述  128K x16 bit Super Low Power and Low Voltage Full CMOS Static RAM
PDF  11 Pages
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制造商  EMLSI [Emerging Memory & Logic Solutions Inc]
网页  http://www.emlsi.com
标志 EMLSI - Emerging Memory & Logic Solutions Inc

EM7640FS16AW45LL 数据表(HTML) 5 Page - Emerging Memory & Logic Solutions Inc

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EM620FU16 Series
Low Power, 128Kx16 SRAM
5
merging Memory & Logic Solutions Inc.
merging Memory & Logic Solutions Inc.
Parameter
Symbol
55ns
70ns
Unit
Min
Max
Min
Max
Read cycle time
tRC
55
-
70
-
ns
Address access time
tAA
-
55
-
70
ns
Chip select to output
tco1, tco2
-
55
-
70
ns
Output enable to valid output
tOE
-
30
-
35
ns
UB, LB acess time
tBA
55
70
ns
Chip select to low-Z output
tLZ1, tLZ2
10
-
10
-
ns
UB, LB enable to low-Z output
tBLZ
10
-
10
-
ns
Output enable to low-Z output
tOLZ
5
-
5
-
ns
Chip disable to high-Z output
tHZ1, tHZ2
0
20
0
25
ns
UB, LB disable to high-Z output
tBHZ
0
20
0
25
ns
Output disable to high-Z output
tOHZ
0
20
0
25
ns
Output hold from address change
tOH
15
-
15
-
ns
Parameter
Symbol
55ns
70ns
Unit
Min
Max
Min
Max
Write cycle time
tWC
55
-
70
-
ns
Chip select to end of write
tCW1, tCW2
45
-
60
-
ns
Address setup time
tAs
0
-
0
-
ns
Address valid to end of write
tAW
45
-
60
-
ns
UB, LB valid to end of write
tBW
45
-
60
-
ns
Write pulse width
tWP
45
-
55
-
ns
Write recovery time
tWR
0
-
0
-
ns
Write to ouput high-Z
tWHZ
0
20
0
25
ns
Data to write time overlap
tDW
25
30
ns
Data hold from write time
tDH
0
-
0
-
ns
End write to output low-Z
tOW
5
-
5
-
ns
READ CYCLE (Vcc =2.7 to 3.3V, Gnd = 0V, TA = -40
oC to +85oC)
WRITE CYCLE (Vcc =2.7 to 3.3V, Gnd = 0V, TA = -40
oC to +85oC)
AC OPERATING CONDITIONS
Test Conditions (Test Load and Test Input/Output Reference)
Input Pulse Level : 0.4 to 2.2V
Input Rise and Fall Time : 5ns
Input and Output reference Voltage : 1.5V
Output Load (See right) : CL = 100pF+ 1 TTL
CL1) = 30pF + 1 TTL
1. Including scope and Jig capacitance
2. R1=3070Ω,
R2=3150Ω
3. VTM=2.8V
CL
1)
VTM
3)
R1
2)
R2
2)



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