ST9293

FUNCTIONAL DESCRIPTION

®

This is Preliminary Data from SGS-THOMSON. Details are subject to change without notice.

May 1993

48K ROM HCMOS MCUs WITH

ON SCREEN DISPLAY AND A/D CONVERTER

Register oriented 8/16 bit CORE with

RUN, WFI and HALT modes

Minimum instruction cycle time: 500ns

(12MHz internal)

16 to 48K bytes of ROM,

256 to 768 bytes of RAM,

224 general purpose registers available as RAM,

accumulators or index registers (Register File)

42-lead Shrink DIP package

Interrupt handler and Serial Peripheral Interface

as standard features

31 fully programmable I/O pins

34 character x15 rows software programmable

On Screen Display module with colour, italic, un-

derline, flash, transparent and fringe attribute

options

16 bit Timer with 8 bit Prescaler, able to be used

as a Watchdog Timer

16-bit programmable Slice Timer with 8-bit pres-

caler

4 channel Analog to Digital Converter, with inte-

gral sample and hold, fast 5.75

µs conversion

time, 6-bit guaranteed resolution

Rich Instruction Set and 14 Addressing modes

Division-by-Zero trap generation

Versatile Development tools, including assembler,

linker, C-compiler, archiver, graphic oriented de-

bugger and hardware emulators

Real Time Operating System

Windowed EPROM parts available for prototyp-

ing and pre-production development phases

Device

ROM

RAM

PACKAGE

ST9293J7

48K

768

PSDIP42

ST9293J5

32K

640

PSDIP42

ST9293J3

24K

512

PSDIP42

ST9293J1

16K

256

PSDIP42

DEVICE SUMMARY

PSDIP42

(Ordering Information at the end of the Datasheet)

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