AI00878C

11 0 An

A0

Qn

Q0

DATA OUT

D

S

Q

READ

S

WRITE

ADDR

OP

CODE

1 0

An

A0

DATA IN

D

Q

OP

CODE

Dn

D0

1

BUSY

READY

S

ERASE

WRITE

ENABLE

1

0

Xn X0

D

OP

CODE

1

01

S

ERASE

WRITE

DISABLE

1

0

Xn X0

D

OP

CODE

00

0

CHECK

STATUS

ADDR

Figure 6. READ, WRITE, EWEN, EWDS Sequences

(Q = 0) will be returned if S is driven high, and the

ST93C56 will ignore any data on the bus. When the

write cycle is completed, the Ready signal (Q = 1)

will indicate (if S is driven high) that the ST93C56

is ready to receive a new instruction. Programming

is internally self-timed (the external clock signal on

C input may be disconnected or left running after

the start of a programming cycle) and does not

require an Erase instruction prior to the Write in-

struction (The Write instruction includes an auto-

matic erase cycle before programing data).

Notes: 1. An: n = 7 for x16 org. and 8 for x8 org.

2. Xn: n = 5 for x16 org. and 6 for x8 org.

7/13

ST93C56/56C, ST93C57C