POWER-ON DATA PROTECTION

In order to prevent data corruption and inadvertent

write operations during power up, a Power On

Reset (POR) circuit resets all internal programming

circuitry and sets the device in the Write Disable

device is properlyreset (in the Write Disable mode)

and is ready to decode and execute an incoming

any logic signal.

INSTRUCTIONS

The ST93CS46/47 has eleven instructions, as

shown in Table 6. Each instruction is preceded by

the rising edge of the signal applied on the Chip

Select (S) input (assuming that the Clock C is low),

followed by a ’1’ read on D input during the rising

edge of the clock C. The op-codes of the instruc-

tions are made up of the 2 following bits. Some

instructions use only these first two bits, others use

also the first two bits of the address field to define

the op-code. The address field is six bits long

(A5-A0).

The ST93CS46/47 is fabricated in CMOS technol-

ogy and is therefore able to run from zero Hz (static

input signals) up to the maximum ratings (specified

in Table 5).

Read

The Read instruction (READ) outputs serial data

on the Data Output (Q). When a READ instruction

is received, the instruction and address are de-

coded and the data from the memory is transferred

into an output shiftregister. A dummy ’0’ bit is output

first followed by the 16 bit word with the MSB first.

Instruction

Description

W

Pin

(1)

PRE

Pin

Op

Code

Address

(1)

Data

Additional

Information

READ

Read Data from Memory

X

’0’

10

A5-A0

Q15-Q0

WRITE

Write Data to Memory

’1’

’0’

01

A5-A0

D15-D0

Write is executed if

the address is not

inside the Protected

area

PAWRITE

Page Write to Memory

’1’

’0’

11

A5-A0

D15-D0

Write is executed if

all the addresses

are not inside the

Protected area

WRALL

Write All Memory

’1’

’0’

00

01XXXX

D15-D0

Write all data if the

Protect Register is

cleared

WEN

Write Enable

’1’

’0’

00

11XXXX

WDS

Write Disable

X

’0’

00

00XXXX

PRREAD

Protect Register Read

X

’1’

10

XXXXXX

Q8-Q0

Data Output =

Protect Register

content + Protect

Flag bit

PRWRITE

Protect Register Write

’1’

’1’

01

A5-A0

Data above

specified address

A5-A0 are protected

PRCLEAR

Protect Register Clear

’1’

’1’

11

111111

Protect Flag is also

cleared (cleared

Flag = 1)

PREN

Protect Register Enable

’1’

’1’

00

11XXXX

PRDS

Protect Register Disable

’1’

’1’

00

000000

OTP bit is set

permanently

Note: 1. X = don’t care bit.

Table 6. Instruction Set

6/16

ST93CS46, ST93CS47