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STA014T 数据表(PDF) 19 Page - STMicroelectronics

部件名 STA014T
功能描述  MPEG 2.5 LAYER III AUDIO DECODER WITH ADPCM AND SRS WOWO POSTPROCESSING CAPABILITY
PDF  45 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STA014T 数据表(HTML) 19 Page - STMicroelectronics

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ADPCM_DATA BUFFER
Address: 0x40 - 0x51 (64 - 81)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
ENCODED DATA N to N+18
ANCCOUNT_L
Address: 0x41 (65)
Type: RO
Software Reset: 0x00
Hardware Reset: 0x00
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
ANCCOUNT_H
Address: 0x42 (66)
Type: RO
Software Reset: 0x00
Hardware Reset: 0x00
ANCCOUNT_H
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
AC15 AC14 AC13 AC12 AC11 AC10
AC9
AC8
ANCCOUNT registers are logically concatenated
and indicate the number of Ancillary Data bits
available at every correctly decoded MPEG
frame.
HEAD_H[23:16]
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
X
X
X
H20
H19
H18
H17
H16
x = don’t care
HEAD_M[15:8]
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
H15
H14
H13
H12
H1‘1
H10
H9
H8
HEAD_L[7:0]
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
H7
H6
H5
H4
H3
H2
H1
H0
Address: 0x43, 0x44, 0x45 (67, 68, 69)
Type: RO
Software Reset: 0x00
Hardware Reset: 0x00
Head[1:0] emphasis
Head[2] original/copy
Head[3] copyrightHead
[5:4] mode extension
Head[7:6] mode
Head[8] private bit
Head[9] padding bit
Head[11:10] sampling frequency index
Head[15:12] bitrate index
Head[16] protection bit
Head[18:17] layer
Head[19] ID
Head[20] ID_ex
The HEAD registers can be viewed as logically
concatenated to store the MPEG Layer III Header
content. The set of three registers is updated
every time the synchronisation to the new MPEG
frame is achieved
The meaning of the flags are shown in the follow-
ing tables:
MPEG IDs
IDex
ID
0
0
MPEG 2.5
0
1
reserved
1
0
MPEG 2
1
1
MPEG 1
Layer
in Layer III these two flags must be set always to
"01".
Protection_bit
It equals "1" if no redundancy has been added
and "0" if redundancy has been added.
STA014-STA014B-STA014T
19/45



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