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STMicroelectronics Solutions for ADSL Line Interfaces

TA0313

As Vo° equals Vo without loading, the gain in this case becomes:

The gain for the loaded system will be:

Equation 1

As shown in Figure 9, this system is an ideal generator, with a synthesized impedance equal to the

internal impedance of the system. Therefore, the output voltage becomes:

Equation 2

with Ro the synthesized impedance and Iout the output current. On the other hand Vo can be expressed

as:

Equation 3

By identifying of both Equation 2 and Equation 3, the synthesized impedance is, with Rs1=Rs2=Rs:

Equation 4

Unlike the level of Vo° required for passive impedance, Vo° will be smaller than 2Vo in this case. Let us

write Vo°=kVo with k the matching factor varying between 1 and 2. Assuming that the current through R3

is negligible, the resistance divider becomes:

After choosing the k factor, Rs will equal to 1/2RL(k-1).

Figure 9: Equivalent schematic, where Ro is the synthesized impedance

G

Vo nol oa d

()

Vi

---------------------------------

1

2R2

R1

-----------

R2

R3

--------

++

1

R2

R3

--------

–

------------------------------------

==

GL

Vo w ithl oad

()

Vi

--------------------------------------

1

2

---

1

2 R2

R 1

-----------

R2

R3

--------

++

1

R2

R3

--------

–

------------------------------------

==

Vo

ViG

()

Ro Io ut

()

–

=

Vo

Vi 1

2R2

R1

-----------

R 2

R 3

--------

++





1

R2

R3

--------

–

------------------------------------------------

Rs1Io ut

1

R 2

R 3

--------

–

-----------------------

–

=

Ro

Vi.Gi

Iout

1/2

RL

Ro

Rs

1

R2

R3

-------

–

-----------------

=

Ro

kVoR L

RL

2Rs1

+

-----------------------------

=