DSP56F826 datasheet(13/60 Pages) FREESCALE

13 / 60 page

Signals and Package Information

56F827 Technical Data, Rev. 12

Freescale Semiconductor

(GPIOG0)

125

Input/Output

Data Bus—D0–D15 specify the data for external Program or Data memory

accesses. D0-D15 are tri-stated when the external bus is inactive.

Port G GPIO—These 16 General Purpose I/O (GPIO) pins can be individually

programmed as input or output pins.

After reset, the default state is Address Bus.

(GPIOG1)

126

(GPIOG2)

127

(GPIOG3)

128

(GPIOG4)

(GPIOG5)

(GPIOG6)

(GPIOG7)

(GPIOG8)

(GPIOG9)

D10

(GPIOG10)

D11

(GPIOG11)

D12

(GPIOG12)

D13

(GPIOG13)

D14

(GPIOG14)

D15

(GPIOG15)

(PCS0)

Output

Program Memory Select—PS is asserted low for external program memory

access. This pin can also be programmed as a programmable chip select.

(PCS1)

Output

Data Memory Select—DS is asserted low for external Data memory access.

This pin can also be programmed as a programmable chip select.

Table 2-2 56F827 Signal and Package Information for the 128 Pin LQFP (Continued)

Signal Name

Pin No.

Type

Description

DSP56F826 数据表(PDF) 13 Page - Freescale Semiconductor, Inc

DSP56F826 数据表(HTML) 13 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

数据表下载