ADS5463IPFPR datasheet(6/37 Pages) TI

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CLK

OVR

[11:0],

N+1

N+5

CLKL

DRY

DATA

CLKH

D[11:0], OVR

CLK

N+2

N+3

N+4

DRY

(1)

N+1

N–1

Sample

N–1

Latency = 3.5 Clock Cycles

TIMING CHARACTERISTICS

(1)

ADS5463

SLAS515B – NOVEMBER 2006 – REVISED MAY 2008 .................................................................................................................................................... www.ti.com

(1)

Polarity of DRY is undetermined. For further information, see the Digital Outputs section.

Figure 1. Timing Diagram

Typical values at TA = 25°C, Min and Max values over full temperature range TMIN = –40°C to TMAX = 85°C, sampling rate =

500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 3-VPP differential clock (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Aperture delay

200

Aperture jitter, rms

150

Latency

3.5

cycles

tCLK

Clock period

tCLKH

Clock pulse duration, high

tCLKL

Clock pulse duration, low

Zero crossing, 10-pF parasitic loading to GND on each

tDRY

CLK to DRY delay(2)

950

1600

output pin

Zero crossing, 10-pF parasitic loading to GND on each

tDATA

CLK to DATA/OVR delay(2)

750

2100

output pin

tDATA – tDRY, 10-pF parasitic loading to GND on each output

tSKEW

DATA to DRY skew

–350

650

tRISE

DRY/DATA/OVR rise time

10-pF parasitic loading to GND on each output pin

500

tFALL

DRY/DATA/OVR fall time

10-pF parasitic loading to GND on each output pin

500

(1)

Timing parameters are specified by design or characterization, but not production tested.

(2)

DRY, DATA, and OVR are updated on the falling edge of CLK. The latency must be added to tDATA to determine the overall propagation

delay.

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