AD7262

Rev. 0 | Page 26 of 32

CS

SCLK

15

19

THREE-STATE

23

4

20

THREE-

STATE

18

21

22

29

30

31

THREE-STATE

THREE-

STATE

FIRST DATA BIT CLOCKED OUT

FIRST DATA BIT READ

CS

30

31

29

21

20

19

18

THREE-STATE

THREE-

STATE

SCLK

12

43

44

45

CS

SCLK

1

5

19

THREE-STATE

2

34

20

THREE-

STATE

18

21

29

30

31

THREE-STATE

THREE-

STATE

FIRST DATA BIT CLOCKED

OUT ON THIS EDGE

FIRST DATA BIT READ

ON THIS EDGE

Figure 35. Serial Interface Timing Diagram When Reading Data on the Falling SCLK Edge with a Slow SCLK Frequency