Preliminary Technical Data

AD8363

Rev. PrB | Page 11 of 14

Table 4. Pin Function Descriptions

Component

Function/Notes

Default Value

C6, C10, C11,

C12

Input:

The AD8363 was designed to be driven single ended. At frequencies below 2.6 GHz, more

dynamic range can be achieved by driving Pin 14 (INHI). In order to do this, C10 and C12

should be populated with an appropriate valued capacitor for the frequency of operation. C6

and C11 should be left open. For frequencies above 2.6 GHz, greater dynamic range can be

achieved by Driving Pin 15 (INLO). This can be done by using an appropriate valued capacitor

for C6 and C11, while leaving C10 and C12 open.

C10=0.1uF, C12=0.1uF,

C6=Open, C11=Open

R7, R10, R11

VTGT:

R10 and R11 are set up to provide 1.4V to VTGT from VREF. An external voltage can be used if

R10 and R11 are removed.

R10=845Ω, R11= 1.4KΩ

C4, C5, C7, C13,

R14, R16

Power Supply Decoupling:

The nominal supply decoupling consists of a 100 pF filter capacitor placed physically close to

the AD8363, a 0 Ω series resistor, and a 0.1 uF capacitor placed closer to the power supply

input pin. The 0 Ω resistor can be replaced with a larger value resistor to add more filtering, at

the expense of a voltage drop.

C4=100 pF, C5=100 pF,

C7= 0.1uF, C13= 0.1uF,

R14= 0 Ω, R16= 0 Ω

R1, R2, R6, R13,

R15

Output Interface--Measurement Mode:

In measurement mode, a portion of the output voltage is fed back to the VSET pin via R6. The

back to VSET, using a voltage divider created by R6 and R2 . If a fast responding output is

expected, the 0 Ω resistor on R15 can be removed to reduce parasitics on the output.

R1=0 Ω, R2=Open,

R6=0 Ω, R13 = Open ,

R15 = 0 Ω

Output Interface--Controller Mode:

In this mode, R6 must be open and R13 must have a 0 Ω resistor. In controller mode, the

AD8363 can control the gain of an external component. A setpoint voltage is applied to the

VSET pin, the value of which corresponds to the desired RF input signal level applied to the

AD8363 RF input. If a fast responding output is expected, the 0 Ω resistor on R15 can be

removed to reduce parasitics on the output.

C9, C8, R5

Low-pass filter capacitors:

The low-pass filter capacitors reduce the noise on the output and affect the pulse response

time of the AD8363. The smallest CLPF capacitance should be 400 pF

C8=Open, C9=0.1uF,

R5=0 Ω

C3

CHPF capacitor

The CHPF capacitor introduces a high-pass filter effect into the AD8363 transfer function and

can affect the response time. It should be tied to VPOS.

C3= 2700 pF

R9, R12

TCM2/PWDN:

The TCM2/PWDN pin controls the amount of nonlinear intercept temperature compensation

and/or shuts down the device. The evaluation board is configured to control this from a test

loop but VREF can be used through a voltage divider created from R9 and R12.

R9= Open, R12= Open

R17, R18

TCM1:

TCM1 controls the intercept temperature compensation (3K impedance). The evaluation board

is configured to control this from a test loop but VREF can be used through a voltage divider

created from R17 and R18

R17=Open, R18=Open

Paddle

The paddle should be tied to both a thermal and electrical ground