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ADE5169 数据表(PDF) 13 Page - Analog Devices |
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ADE5169 数据表(HTML) 13 Page - Analog Devices |
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13 / 148 page  Preliminary Technical Data ADE5166/ADE5169/ADE5566/ADE5569 Rev. PrB | Page 13 of 148 Table 9. SPI Slave Mode Timing (SPICPHA = 1) Parameters Parameter Description Min Typ Max Unit tSS SS to SCLK edge 145 ns tSL SCLK low pulse width 6 × tCORE1 ns tSH SCLK high pulse width 6 × tCORE1 ns tDAV Data output valid after SCLK edge 25 ns tDSU Data input setup time before SCLK edge 0 ns tDHD Data input hold time after SCLK edge 2 × tCORE1 + 0.5 μs μs tDF Data output fall time 19 ns tDR Data output rise time 19 ns tSR SCLK rise time 19 ns tSF SCLK fall time 19 ns tSFS SS high after SCLK edge 0 ns 1 tCORE depends on the clock divider or CD[2:0] bits of the POWCON SFR (see Table 25); tCORE = 2CD/4.096 MHz. MSB MOSI BITS [6:1] tDHD tDSU MSB IN LSB IN BITS [6:1] LSB tDR tDF tDAV MISO tSL tSH tSR tSF tSFS tSS SCLK (SPICPOL = 1) SCLK (SPICPOL = 0) SS Figure 7. SPI Slave Mode Timing (SPICPHA = 1) |
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