ADL5592

Rev. 0 | Page 12 of

20

APPLICATIONS INFORMATION

LOIP

LOIN

VCC

LOOP OUT

LOOP EN

DATA

CLK

LE

DVCC

GND

NC

GND

GND

GND

NC

NC

NC

GND

GND

VCC

ADL5592

100pF

1000pF

1000pF

0.1µF

100pF

10µF

100pF

0.1µF

0.1µF

0.1µF

1000pF

LO INPUT

VPOS

LOOP OUT

MIXER ENABLE

RF OUTPUT

RF INPUT

VPOS

SPI DATA

SPI CLOCK

SPI LATCH

VPOS

CHOKE INDUCTOR (COILCRAFT 0603CS)

33nH FOR 1800MHz, 1900MHz BANDS

270nH FOR 450MHz, 850MHz, 900MHz BANDS

Figure 17. Basic Connections

BASIC CONNECTIONS

Figure 17 shows the basic connections for the ADL5592. A

single power supply between 4.75 V and 5.25 V is applied to

the VCC pins. All the VCC pins must be connected to the same

potential. Each power supply pin should be decoupled using a

100 pF capacitor in addition to either a 0.1 μF or 10 μF capacitor.

These capacitors should be located as close as possible to the

device. One of the supply pins (Pin 21) also requires biasing of

an open-collector using an RF choke (Coilcraft 0603CS). The

value of the inductor is dictated by the frequency band of

operation: 270 nH for the 450 MHz, 850 MHz, and 900 MHz

bands and 33 nH for the 1800 MHz and 1900 MHz bands. The

RFIN, RFOUT, and LOOP OUT pins have 50 Ω impedances

and must be ac-coupled.

PROGRAMMING THE SPI PORT

Both attenuators are programmed with a single 10-bit word.

Figure 18 shows the input and output attenuators, ATTN 1 and

ATTN 2, respectively. Table 4 lists the 10-bit words corresponding

to the various gain levels. The five least significant bits (LSBs)

set the input attenuator, ATTN 1. The five most significant bits

(MSBs) set the output attenuator, ATTN 2.

RFIN

RFOUT

ATTN 1

AMP

ATTN 2

Figure 18. Block Diagram of Attenuator Chain

Figure 19 shows the timing diagram of the SPI port transmission.

DATA is clocked on the rising edge of CLK. The data is latched

and the attenuation is updated on the falling edge of LE (the latch

enable pin). The timing requirements indicated in Figure 19 are

described in Table 5.