21

AT89C55WD

1921B–MICRO–09/02

Program

Memory Lock

Bits

The AT89C55WD has three lock bits that can be left unprogrammed (U) or can be pro-

grammed (P) to obtain the additional features listed in the following table.

When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during

reset. If the device is powered up without a reset, the latch initializes to a random value and

holds that value until reset is activated. The latched value of EA must agree with the current

logic level at that pin in order for the device to function properly.

Programming

the Flash

The AT89C55WD is shipped with the on-chip Flash memory array ready to be programmed.

The programming interface needs a high-voltage (12-volt) program enable signal and is com-

patible with conventional third-party Flash or EPROM programmers.

The AT89C55WD code memory array is programmed byte-by-byte.

Programming Algorithm: Before programming the AT89C55WD, the address, data, and

control signals should be set up according to the Flash programming mode table and Figures

13 and 14. To program the AT89C55WD, take the following steps:

1.

Input the desired memory location on the address lines.

2.

Input the appropriate data byte on the data lines.

3.

Activate the correct combination of control signals.

4.

Raise EA/V

5.

Pulse ALE/PROG oncetoprogram a byteinthe Flasharray or thelock bits. Thebyte-

write cycle is self-timed and typically takes no more than 50 µs. Repeat steps 1

through 5, changing the address and data for the entire array or until the end of the

object file is reached.

Chip Erase Sequence: Before the AT89C55WD can be reprogrammed, a Chip Erase opera-

tion needs to be performed. To erase the contents of the AT89C55WD, follow this sequence:

1.

Raise V

2.

Pulse ALE/PROG once (duration of 200 - 500 ns).

3.

Wait for 150 ms.

4.

5.

Pulse ALE/PROG once (duration of 200 - 500 ns).

6.

Wait for 150 ms.

7.

Power V

Data Polling: The AT89C55WD features Data Polling to indicate the end of a write cycle. Dur-

ing a write cycle, an attempted read of the last byte written will result in the complement of the

written data on P0.7. Once the write cycle has been completed, true data is valid on all out-

Table 9. Lock Bit Protection Modes

Program Lock Bits

Protection Type

LB1

LB2

LB3

1

U

U

U

No program lock features.

2P

U

U

MOVC instructions executed from external program memory are

disabled from fetching code bytes from internal memory, EA is

sampled and latched on reset, and further programming of the Flash

memory is disabled.

3

P

P

U

Same as mode 2, but verify is also disabled.

4

P

P

P

Same as mode 3, but external execution is also disabled.