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AT89C5132-ROTUL 数据表(PDF) 14 Page - ATMEL Corporation |
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AT89C5132-ROTUL 数据表(HTML) 14 Page - ATMEL Corporation |
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14 / 182 page  14 4173E–USB–09/07 AT89C5132 Figure 6-4. PLL Block Diagram and Symbol Figure 6-5. PLL Filter Connection 6.3.2 PLL Programming The PLL is programmed using the flow shown in Figure 6-6. As soon as clock generation is enabled, the user must wait until the lock indicator is set to ensure the clock output is stable. The PLL clock frequency will depend on the audio interface clock frequencies. Figure 6-6. PLL Programming Flow 6.4 Registers Table 1. CKCON Register PLLEN PLLCON.1 N6:0 N divider R divider VCO PLLclk OSCclk R 1 + ( ) × N 1 + ----------------------------------------------- = OSC CLOCK PFLD PLOCK PLLCON.0 PFILT CHP Vref Up Down R9:0 PLL CLOCK PLL Clock Symbol PLL Clock VSS PFILT R C1 C2 VSS PLL Programming Configure Dividers N6:0 = xxxxxxb R9:0 = xxxxxxxxxxb Enable PLL PLLRES = 0 PLLEN = 1 PLL Locked? PLOCK = 1? |
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