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ADE7566 数据表(PDF) 49 Page - Analog Devices

部件名 ADE7566
功能描述  Single-Phase Energy Measurement IC with 8052 MCU, RTC and LCD driver
PDF  148 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADE7566 数据表(HTML) 49 Page - Analog Devices

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Preliminary Technical Data
ADE75xx/ADE71xx
Rev. PrE | Page 49 of 148
sensor, the resulting magnitude and phase response should be a
flat gain over the frequency band of interest. The di/dt sensor
has a 20 dB/dec gain associated with it. It also generates signifi-
cant high frequency noise, therefore a more effective anti-
aliasing filter is needed to avoid noise due to aliasing—see the
Anti-aliasing Filter section.
When the digital integrator is switched off, the
ADE75xx/ADE71xx can be used directly with a conventional
current sensor such as a current transformer (CT) or with a low
resistance current shunt.
POWER QUALITY MEASUREMENTS
Zero-Crossing Detection
The ADE75xx/ADE71xx has a zero-crossing detection circuit
on the voltage channel. This zero crossing is used to produce an
external zero-crossing signal (ZX), and it is also used in the
calibration mode.
The zero-crossing is generated, by default, from the output of
LPF1. As explained in the following paragraph, this filter has a
low cut-off frequency and is intended for use for 50 and 60Hz
system. If needed this filter can be disabled to allow a higher
frequency signal to be detected or to limit the group delay of the
detection. If the voltage input fundamental frequency is below
60Hz and a time delay in ZX detection is acceptable, it is
recommended to enable LPF1. Enabling LPF1 will limit the
variability in the ZX detection by eliminating the high
frequency components.
Figure 29 shows how the zero-crossing signal is generated.
x1, x2, x4,
x8, x16
ADC 2
REFERENCE
LPF1
f3dB = 63.7Hz
PGA2
{GAIN [7:5]}
VP
VN
V2
ZERO
CROSS
ZX
HPF
MODE1[6]
43.24° @ 60Hz
1.0
0.73
ZX
V2
LPF1
Figure 29. Zero-Crossing Detection on Voltage channel
The zero-crossing signal ZX is generated from the output of
LPF1 (bypassed or not). LPF1 has a single pole at 63.7 Hz (at
MCLK = 4.096 MHz). As a result, there is a phase lag between
the analog input signal V2 and the output of LPF1. The phase
lag response of LPF1 results in a time delay of approximately
2 ms (@ 60 Hz) between the zero crossing on the analog inputs
of the voltage channel and ZX detection.
The zero-crossing detection also drives the ZX flag in the
Interrupt Status Register 3 SFR (MIRQSTH, 0xDE). If the ZX
bit in the Interrupt Enable Register 3 SFR (MIRQENH, 0xDB) is
set, the 8052 core has a pending ADE interrupt.
The ADE interrupt stays active until the ZX status bit is
cleared—see Energy measurement interrupts section.
Zero-Crossing Timeout
The zero-crossing detection also has an associated timeout
register, ZXTOUT. This unsigned, 12-bit register is decremented
(1 LSB) every 160/MCLK seconds. The register is reset to its
user programmed full-scale value every time a zero crossing is
detected on the voltage channel. The default power on value in
this register is 0xFFF. If the internal register decrements to 0
before a zero crossing is detected and the ZXTOUT flag in the
Interrupt Status Register 3 SFR (MIRQSTH, 0xDE) is set. If the
ZXTO bit in the Interrupt Enable Register 3 SFR (MIRQENH,
0xDB) is set, the 8052 core has a pending ADE interrupt.
The ADE interrupt stays active until the ZXTO status bit is
cleared—see Energy measurement interrupts section.
The ZXOUT register (Address 0x11) can be written or read by
the user—see Energy Measurement Register List. The resolution
of the register is 160/MCLK seconds per LSB. Thus the maxi-
mum delay for an interrupt is 0.16 second (128/MCLK × 212)
when MCLK = 4.096MHz.
Figure 30 shows the mechanism of the zero-crossing timeout
detection when the line voltage stays at a fixed dc level for more
than CLKIN/160 × ZXTOUT seconds.
12-BIT INTERNAL
REGISTER VALUE
ZXTOUT
VOLTAGE
CHANNEL
ZXTO
FLAG
BIT
Figure 30. Zero-Crossing Timeout Detection
Period or Frequency Measurements
The ADE75XX/ADE71XX provides the period or frequency
measurement of the line. The period or frequency measurement
is selected by clearing or setting FREQSEL bit in the MODE2
register (0x0C). The period/frequency register is an unsigned
16-bit register and is updated every period. If LPF1 is enabled, a
settling time of 1.8 seconds is associated with this filter before
the measurement is stable.



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