T80C5112-RKFIV datasheet(6/97 Pages) ATMEL

6 / 97 page

Rev. B - November 10, 2000

Preliminary

T80C5112

I/O

AIN3 (P4.3): A/D converter input 3

INT1: External interrupt 1

I/O

AIN4 (P4.4): A/D converter input 4

MISO: Master IN, Slave OUT of the SPI controller

I/O

AIN5 (P4.5): A/D converter input 5

MOSI: Master OUT, Slave IN of the SPI controller

I/O

AIN6 (P4.6): A/D converter input 6

SPSCK: Clock I/O of the SPI controlle

I/O

AIN7 (P4.7): A/D converter input 7

P0.0-P0.7

I/O

Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s

written to them ßoat and can be used as high impedance inputs. Port 0 is also

the multiplexed low-order address and data bus during access to external program

and data memory. In this application, it uses strong internal pull-up when emitting

1s.

P2.0-P2.7

I/O

Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2

pins that have 1s written to them are pulled high by the internal pull-ups and

can be used as inputs. As inputs, Port 2 pins that are externally pulled low will

source current because of the internal pull-ups. Port 2 emits the high-order address

byte during fetches from external program memory and during accesses to external

data memory that use 16-bit addresses (MOVX @DPTR).In this application, it

uses strong internal pull-ups emitting 1s. During accesses to external data memory

that use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR.

RST

RST: A high on this pin for two machine cycles while the oscillator is running,

resets the device. An internal diffused resistor to VSS permits a power-on reset

using only an external capacitor to VCC. If the hardware watchdog reaches its

time-out, the reset pin becomes an output during the time the internal reset is

activated.

ALE

Address Latch Enable: Output pulse for latching the low byte of the address

during an access to external memory. In normal operation, ALE is emitted at a

constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency, and can be used

for external timing or clocking. Note that one ALE pulse is skipped during each

access to external data memory. ALE can be disabled by setting SFRÕs AUXR.0

bit. With this bit set, ALE will be inactive during internal fetches.

PSEN

Program Store ENable: The read strobe to external program memory. When

executing code from the external program memory, PSEN is activated twice each

machine cycle, except that two PSEN activations are skipped during each access

to external data memory. PSEN is not activated during fetches from internal

program memory.

External Access Enable: EA must be externally held low to enable the device

to fetch code from external program memory locations 0000H and 1FFFH . If

EA is held high, the device executes from internal program memory unless the

program counter contains an address greater than 1FFFH. EA must be held low

for ROMless devices. If security level 1 is programmed, EA will be internally

latched on Reset.

XTAL1

XTAL1 : Input to the inverting oscillator amplifier and input to the internal

clock generator circuits, selected by hardware set upb

XTAL2

XTAL2 : Output from the inverting oscillator amplifier, selected by hardware

set up

Hardware set up :

+Configuration bits programmed with the code for ROM version

+Configuration bits for EPROM version

Hardware set up :

+Configuration bits programmed with the code for ROM version

+Configuration bits for EPROM version

T80C5112-RKFIV 数据表(PDF) 6 Page - ATMEL Corporation

T80C5112-RKFIV 数据表(HTML) 6 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97

数据表下载