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XC2000 数据表(PDF) 21 Page - Infineon Technologies AG |
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XC2000 数据表(HTML) 21 Page - Infineon Technologies AG |
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21 / 729 page  XC2000 Derivatives Peripheral Units (Vol. 2 of 2) The General Purpose Timer Units Preliminary User’s Manual 14-3 V1.0, 2007-06 GPT_X7, V2.0 The interrupts of GPT1 are controlled through the Interrupt Control Registers TxIC. These registers are not part of the GPT1 block. The input and output lines of GPT1 are connected to pins of ports P3 and P5. The control registers for the port functions are located in the respective port modules. Note: The timing requirements for external input signals can be found in Section 14.1.5, Section 14.3 summarizes the module interface signals, including pins. Figure 14-2 GPT1 Block Diagram (n = 2 … 5) T3 Mode Control 2n: 1 fGPT T2 Mode Control Aux. Timer T2 Reload Capture T4 Mode Control Aux. Timer T4 Reload Capture Core Timer T3 T3OTL U/D T2EUD T2IN T3IN T3EUD T4IN T4EUD Toggle Latch U/D U/D Interrupt Request (T2IRQ) Interrupt Request (T3IRQ) Interrupt Request (T4IRQ) mc_gpt0101_bldiax1.vsd T3OUT Basic clock T3CON.BPS1 |
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