HT80C51 User Manual
Peripheral Modules – Standard Serial Interface (SIO0)
Handshake Solutions
© Philips Electronics N.V. 2005
Page 39 of 132
SBUF read only
SBUF write only
HT-SFR bus
sio_rxd_i
sio_txd_o
TI
>=1
RI
>=1
int[4]
sio_clk_i
sio_active_o
sio_clk_o
SEND
RECEIVE
>=1
not SEND
TB8
1/16
1
0
2
1
3
1/2
t1_overflow
mode
sio_mode0_o
0
0
RB8
bit
sampler
start-bit
detector
[Figure 13] Block Diagram of Serial Interface in Mode 1, 2, and 3
Multiprocessor Communications
Modes 2 and 3 have a special provision for multiprocessor communications. In these modes, 9 data
bits are received. The 9th one goes into RB8. Then comes a stop bit. The port can be programmed
such that when the stop bit is received, the serial port interrupt will be activated only if RB8 = 1. This
feature is enabled by setting bit SM2 in SCON. A way to use this feature in multiprocessor systems is as
follows:
When the master processor wants to transmit a block of data to one of several slaves, it first sends out
an address byte that identifies the target slave. An address byte differs from a data byte in that the 9th
bit is 1 in an address byte and 0 in a data byte. With SM2 = 1, no slave will be interrupted by a data
byte. An address byte, however, will interrupt all slaves, so that each slave can examine the received
byte and see if it is being addressed. The addressed slave will clear its SM2 bit and prepare to receive
the data bytes that will be coming.
The slaves that weren’t being addressed leave their SM2s set and go on about their business, ignoring
the coming data bytes.
SM2 has no effect in Mode 0, and in Mode 1 it can be used to check the validity of the stop bit. In a
Mode 1 reception, if SM2 = 1, the receive interrupt will not be activated unless a valid stop bit is re-
ceived.
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