LM3S328 Data Sheet
October 8, 2006
7
Preliminary
List of Figures
Figure 1-1.
Stellaris High-Level Block Diagram ........................................................................................... 23
Figure 1-2.
LM3S328 Controller System-Level Block Diagram ................................................................... 29
Figure 2-1.
CPU Block Diagram .................................................................................................................. 31
Figure 2-2.
TPIU Block Diagram .................................................................................................................. 32
Figure 5-1.
JTAG Module Block Diagram .................................................................................................... 39
Figure 5-2.
Test Access Port State Machine ............................................................................................... 42
Figure 5-3.
IDCODE Register Format.......................................................................................................... 46
Figure 5-4.
BYPASS Register Format ......................................................................................................... 46
Figure 5-5.
Boundary Scan Register Format ............................................................................................... 47
Figure 6-1.
External Circuitry to Extend Reset............................................................................................. 49
Figure 6-2.
Main Clock Tree ........................................................................................................................ 52
Figure 7-1.
Flash Block Diagram ................................................................................................................. 89
Figure 8-1.
GPIO Module Block Diagram .................................................................................................. 104
Figure 8-2.
GPIO Port Block Diagram........................................................................................................ 105
Figure 8-3.
GPIODATA Write Example...................................................................................................... 106
Figure 8-4.
GPIODATA Read Example ..................................................................................................... 106
Figure 9-1.
GPTM Module Block Diagram ................................................................................................. 142
Figure 9-2.
16-Bit Input Edge Count Mode Example ................................................................................. 146
Figure 9-3.
16-Bit Input Edge Time Mode Example...................................................................................147
Figure 9-4.
16-Bit PWM Mode Example .................................................................................................... 148
Figure 10-1.
WDT Module Block Diagram ................................................................................................... 173
Figure 11-1.
ADC Module Block Diagram.................................................................................................... 196
Figure 11-2.
Internal Temperature Sensor Characteristic............................................................................ 199
Figure 12-1.
UART Module Block Diagram.................................................................................................. 227
Figure 12-2.
UART Character Frame........................................................................................................... 228
Figure 13-1.
SSI Module Block Diagram...................................................................................................... 262
Figure 13-2.
TI Synchronous Serial Frame Format (Single Transfer).......................................................... 264
Figure 13-3.
TI Synchronous Serial Frame Format (Continuous Transfer) ................................................. 265
Figure 13-4.
Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................................... 266
Figure 13-5.
Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................................. 266
Figure 13-6.
Freescale SPI Frame Format with SPO=0 and SPH=1........................................................... 267
Figure 13-7.
Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0............................... 267
Figure 13-8.
Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0....................... 268
Figure 13-9.
Freescale SPI Frame Format with SPO=1 and SPH=1........................................................... 268
Figure 13-10. MICROWIRE Frame Format (Single Frame)........................................................................... 269
Figure 13-11. MICROWIRE Frame Format (Continuous Transfer) ............................................................... 270
Figure 13-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements............................ 271
Figure 14-1.
I2C Block Diagram ................................................................................................................... 297
Figure 14-2.
I2C Bus Configuration.............................................................................................................. 298
Figure 14-3.
Data Validity During Bit Transfer on the I2C Bus..................................................................... 298
Figure 14-4.
START and STOP Conditions ................................................................................................. 298
Figure 14-5.
Complete Data Transfer with a 7-Bit Address ......................................................................... 299
Figure 14-6.
R/S Bit in First Byte ................................................................................................................. 300
Figure 14-7.
Master Single SEND................................................................................................................ 300
Figure 14-8.
Master Single RECEIVE.......................................................................................................... 301
Figure 14-9.
Master Burst SEND ................................................................................................................. 302
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