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STE800P

November 2001

This is preliminary information on a new product now in development. Details are subject to change without notice.

REVISION: A06

1.0 DESCRIPTION

The STE800P is a high performance Octal Fast

Ethernet physical layer interface for 10BASE-T and

100BASE-TX/ FX applications.

It was designed with advanced CMOS technology to

provide a RMII/SMII for easy attachment to 10/100

Media Access Controllers (MAC) and a physical me-

dia interface for 100BASE-TX / FX of IEEE802.3u

and 10BASE-T of IEEE802.3.

The STE800P supports both half-duplex and full-du-

plex operation, at 10 and 100 Mbps operation. Its op-

erating mode can be set using auto-negotiation,

parallel detection or manual control. It also allows for

the support of auto-negotiation functions for speed

and duplex detection.

2.0 FEATURE

2.1 Industry standard

• IEEE802.3u 100BASE-TX /FX and IEEE802.3

10BASE-T compliant

• Support for IEEE802.3x flow control

• IEEE802.3u Auto-Negotiation support

• RMII/SMII interface

• Low power, single supply 3.3V CMOS

• Shared MII management interface up to 25

Mbps

PQFP208

ORDERING NUMBER: STE800P

PRODUCT PREVIEW

10/100 BASE-TX/FX 8 PORT TRANSCEIVER

Figure 1. BLOCK DIAGRAM FOR 1 PORT

LEDS

TRANS-

4B/ 5B

Binary to MLT3

Parallel

To

Serial

MITTER

10/100

NRZ To

Manchester

Encoder

Link Pulse

Generator

NRZ To

NRZI

Encoder

10 TX

Filter

TXP

TXN

TX Channel

100Mb/s

HW

SMII_EN

MDIO

MDIC

TXD(1:0)

TX_ER

TX_EN

CRS_DV

REFCLK

RX_ER

RXD(1:0)

Encoder

Scrambler

10Mb/s

RXN

RXP

RX Channel

RECEIVER

10/100

Link Pulse

Detector

10 RX Filter

Clk Recovery

SMART

Squelch

NRZ To

Manchester

Decoder

10Mb/s

Descrambler

Code Align

100Mb/s

4B/ 5B

Serial

To

Parallel

NRZI To

NRZ

Decoder

Adaptive

Equalization

Baseline

Wander

Binary To

MLT3 Decoder

Clock Recovery

HW Config

Power

Down

Pins

Config

Clock

Generation

Loopback

REGISTERS

Auto

Negotiation

System

Clock