M41ST85WMH6F datasheet(26/41 Pages) STMICROELECTRONICS

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Clock operation

M41ST85W

26/41

3.8

Reset inputs (RSTIN1 & RSTIN2)

The M41ST85W provides two independent inputs which can generate an output reset. The

duration and function of these resets is identical to a reset generated by a power cycle.

Table 5 and Figure 17 illustrate the AC reset characteristics of this function. Pulses shorter

than tRLRH1 and tRLRH2 will not generate a reset condition. RSTIN1 and RSTIN2 are each

internally pulled up to VCC through a 100kΩ resistor.

Figure 17.

RSTIN1 & RSTIN2 timing waveforms

Note:

With pull-up resistor

Table 5.

Reset AC characteristics

3.9

Power-fail input/output

The Power-Fail Input (PFI) is compared to an internal reference voltage (1.25V). If PFI is

less than the power-fail threshold (VPFI), the Power-Fail Output (PFO) will go low. This

function is intended for use as an undervoltage detector to signal a failing power supply.

Typically PFI is connected through an external voltage divider (see Figure 5 on page 11) to

either the unregulated DC input (if it is available) or the regulated output of the VCC

regulator. The voltage divider can be set up such that the voltage at PFI falls below VPFI

several milliseconds before the regulated VCC input to the M41ST85W or the

microprocessor drops below the minimum operating voltage.

During battery back-up, the power-fail comparator turns off and PFO goes (or remains) low.

This occurs after VCC drops below VPFD(min). When power returns, PFO is forced high,

irrespective of VPFI for the write protect time (trec), which is the time from VPFD(max) until the

inputs are recognized. At the end of this time, the power-fail comparator is enabled and PFO

Symbol

Parameter(1)

Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 2.7 to 3.6V (except where noted).

Min

Max

Unit

tRLRH1

(2)

Pulse width less than 50ns will result in no RESET (for noise immunity).

RSTIN1 Low to RSTIN1 High

200

tRLRH2

(3)

Pulse width less than 20ms will result in no RESET (for noise immunity).

RSTIN2 Low to RSTIN2 High

100

tR1HRH

(4)

Programmable (see Table 6 on page 28).

RSTIN1 High to RST High

200

tR2HRH

(4)

RSTIN2 High to RST High

200

AI03665

RSTIN2

RST

(1)

RSTIN1

tRLRH1

tRLRH2

tR1HRH

tR2HRH

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