M41T93 datasheet(13/51 Pages) STMICROELECTRONICS

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M41T93

Operation

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2.1

SPI bus characteristics

The serial peripheral interface (SPI) bus is intended for synchronous communication

between different ICs. It consists of four signal lines: serial data input (SDI), serial data

output (SDO), serial clock (SCL) and a chip enable (E).

By definition a device that gives out a message is called “transmitter,” the receiving device

that gets the message is called “receiver.” The device that controls the message is called

“master.” The devices that are controlled by the master are called “slaves.”

The E input is used to initiate and terminate a data transfer. The SCL input is used to

synchronize data transfer between the master (micro) and the slave (M41T93) device.

The SCL input, which is generated by the microcontroller, is active only during address and

data transfer to any device on the SPI bus (see Figure 5 on page 10).

The M41T93 can be driven by a microcontroller with its SPI peripheral running in only mode

0: (CPOL, CPHA) = (0,0).

For this mode, input data (SDI) is latched in by the low-to-high transition of clock SCL, and

output data (SDO) is shifted out on the high-to-low transition of SCL (see Table 2 and

Figure 6 on page 10).

There is one clock for each bit transferred. Address and data bits are transferred in groups

of eight bits. Due to memory size the second most significant address bit is a “don’t care”

(address bit 6).

2.2

Read and write cycles

Address and data are shifted MSB first into the serial data input (SDI) and out of the serial

data output (SDO). Any data transfer considers the first bit to define whether a READ or

WRITE will occur. This is followed by seven bits defining the address to be read or written.

Data is transferred out of the SDO for a READ operation and into the SDI for a WRITE

operation. The address is always the second through the eighth bit written after the enable

(E) pin goes low. If the first bit is a '1,' one or more WRITE cycles will occur. If the first bit is a

'0,' one or more READ cycles will occur (see Figure 7 and Figure 8 on page 14).

Data transfers can occur one byte at a time or in multiple byte burst mode, during which the

address pointer will be automatically incremented. For a single byte transfer, one byte is

read or written and then E is driven high. For a multiple byte transfer all that is required is

that E continue to remain low. Under this condition, the address pointer will continue to

increment as stated previously. Incrementing will continue until the device is deselected by

taking E high. The address will wrap to 00h after incrementing to 3Fh.

The system-to-user transfer of clock data will be halted whenever the address being read is

a clock address (00h to 07h). Although the clock continues to maintain the correct time, this

will prevent updates of time and date during either a READ or WRITE of these address

locations by the user. The update will resume either due to a deselect condition or when the

pointer increments to an non-clock or RAM address (08h to 1Fh).

Note:

This is true both in READ and WRITE mode.

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