STOTG04ES

Block description

17/26

Table 15.

UART drivers direction

6.7.4

Audio mode

In this mode the transceiver has to release all of its drivers and pull-up/pull-down resistors on the D+, D-

and ID pins, leaving them in a high impedance state. This allows these lines to be used for transmission

described in Table 16 force the transceiver into the audio mode.

Table 16.

Audio mode setup

6.8

Registers

The STOTG04ES transceiver device is controlled using register settings (see Table 17). These registers

Table 17.

Register set

(1) Access type can be: read (r), set (s), clear (c).

(2) The first address is to set, the second one to clear bits.

When writing to the set address, any “1” will set the associated Bit to logic “1”. When writing to the clear

address, any “1” will set the associated Bit to logic “0”. It is possible to read from any address, whether it

is a set or clear address. See Tables 18, 19, 20, 21 for bit setting details.

bdir[1]

bdir[0]

DAT_VP

↔ D+

SE0_VM

↔ D-

00

→→

01

→←

10

←→

11

←←

transp_en bit

uart_en bit

OE_TP_INT/ signal

Control Register 2

0

0

1

00000000

Register

Size (bits)

Description

Vendor ID

16

r

00h

STMicroelectronics ID (0483h) - LSB first

Product ID

16

r

02h

ID of the STOTG04 (A0C4h) - LSB first

Control 1

8

r/s/c

04h 05h

First Control Register

Control 2

8

r/s/c

06h 07h

Second Control Register

Control 3

8

r/s/c

12h 13h

Third Control Register

Interrupt Source

8

r

08h

Current state of signals generating interrupts

Interrupt Latch

8

r/s/c

0Ah 0Bh

Latched source that generated interrupt

Interrupt Mask False

8

r/s/c

0Ch 0Dh

Enables interrupts on falling edge

Interrupt Mask True

8

r/s/c

0Eh 0Fh

Enables interrupts on rising edge