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STLC5411 数据表(PDF) 52 Page - STMicroelectronics |
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STLC5411 数据表(HTML) 52 Page - STMicroelectronics |
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52 / 72 page  Table 9: READ BACK MESSAGES FUNCTION BYTE 1 BYTE 2 AD7/4 AD3/1 AD0 7 6 5 4 3 2 1 0 OPR 0010 000 1 CIE EIE FIE OB1 OB0 0C1 0C0 C2E CR1 0010 001 1 FF1 FF0 CK2 CK1 CK0 DDM CMS BEX CR2 0010 010 1 SFS NTS DMO DEN DD BP1 BP2 RR CR3 0010 011 1 LB1 LB2 LBD DB1 DB2 DBD TLB T15D CR4 0010 100 1 EB1 EB2 ED FFIT ESFr CTLIO MOB CTC CR5 0010 101 1 I04 I03 I02 I01 D4 D3 D2 D1 CR6 0010 110 T1SE ACTUAT PUPAUT QM AIS TFB0 RFS LFS TXB1 0011 000 1 0 0 B1X5 B1X4 B1X3 B1X2 B1X1 B1X0 TXB2 0011 001 1 0 0 B2X5 B2X4 B2X3 B2X2 B2X1 B2X0 RXB1 0011 010 1 0 0 B1R5 B1R4 B1R3 B1R2 B1R1 B1R0 RXB2 0011 011 1 0 0 B2R5 B2R4 B2R3 B2R2 B2R1 B2R0 TXD 0011 100 1 DX5 DX4 DX3 DX2 DX1 DX0 SX1 SX0 RXD 0011 101 1 DR5 DR4 DR3 DR2 DR1 DR0 SR1 SR0 TXM4 0100 000 1 0 M42x M43x M44x M45x M46x 0 M48x TXM56 0100 001 1 0 0 0 M51x M61x M52x FEBx FEBx TXACT 0100 010 1 0 0 0 0 C4x C3x C2x C1x BEC1 0100 011 1 c7 c6 c5 c4 c3 c2 c1 c0 BEC2 0100 100 1 c7 c6 c5 c4 c3 c2 c1 c0 ECT1 0100 101 1 ECT17 ECT16 ECT15 ECT14 ECT13 ECT12 ECT11 ECT10 ECT2 0100 110 1 ECT27 ECT26 ECT25 ECT24 ECT23 ECT22 ECT21 ECT20 TXEOC 0110 EFG H XEOC1 XEOC2 XEOC3 XEOC4 XEOC5 XEOC6 XEOC7 XEOC8 IDR 1000 000 0 0 0 0 0 1 0 0 0 Notes: 1. For all these registers with the exception of TXEOC, bit 0 of BYTE 1 is set to 1 to indicate read-back message. 2. CR5 configuration/status register is listed with status registers. 3. Bit 7 of BYT E 1 is the first clocked out from the UID. 4. M42x is significant in NT mode only Table 10: SPONTANEOUS OR DRIVEN MESSAGES FUNCTION BYTE 1 BYTE 2 AD7/4 AD3/1 AD0 7 6 5 4 3 2 1 0 CR5 0010 101 0 IO4 IO3 IO2 IO1 D4 D3 D2 D1 STATUS 0011 111 0 PWDN 0 0 0 RxFFU RxFFO TxFFU TxFFO RXM4 0100 000 0 M41R M42R M43R M44R M45R M46R M47R M48R RXM56 0100 001 0 0 0 0 M51R M61R M52R FEBR NEBR RXACT 0100 010 0 0 0 0 0 C4R C3R C2R C1R BEC1 0100 011 0 c7 c6 c5 c4 c3 c2 c1 c0 BEC2 0100 100 0 c7 c6 c5 c4 c3 c2 c1 c0 RXEOC 0101 EFG H REOC1 REOC2 REOC3 REOC4 REOC5 REOC6 REOC7 REOC8 Notes: 1. All status registers can be read by setting first the appropriate command. At any status change, an interrupt cycle is issued. 2. In the RXEOC register: E = ea1 F = ea2 G = ea3 H = d=0/m = 1 3. For all These registers with the exception of RXEOC, bit 0 of BYTE 1 is set to 0 to indicate a status register. STLC5411 52/72 |
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