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STLC5460 数据表(PDF) 31 Page - STMicroelectronics |
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STLC5460 数据表(HTML) 31 Page - STMicroelectronics |
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31 / 54 page ![]() connected instead of Insert A Register if DCG = 0, and instead of Insert A and Insert B Registers if DCG = 1. When SGV goes to ”1”, the current contents of Command Register (CMD) is taken into account by the generator. In this case, Command Register means : 7 0 0 0 BCH1 BCH0 0 0 ACH1 ACH0 BCH1/0 Insert B channel 1/0. If generator transmits sequence instead of Insert B register, the data rate for this channel is given by BCH1/0 BCH1 BCH0 0 0 8 kb/s 0 1 16 kb/s 1 0 32 kb/s 1 1 64 kb/s ACH1/0 Insert A channel 1/0 If generator transmits sequence instead of insert A Register, the data rate for this channel is given by ACH1/0. ACH1 ACH0 0 0 8 kb/s 0 1 16 kb/s 1 0 32 kb/s 1 1 64 kb/s If DCG = 1, the data rate of PRS generator is the sum of data rate Insert B channel and Insert A channel. If DCG = 0, the data rate of PRS generator is equal to data rate of Insert A channel. ERROR COUNTER REGISTER (ECR) 7 0 EC7 EC6 EC5 EC4 EC3 EC2 EC1 EC0 After RESET 00 (H). If the Pseudo Random Sequence Analyser is validated (SAV = 1), this register indicates the number of errored bits received after the synchronisation of the Pseudo Random Sequence. When Error Counter Register indicates all ”1”s, the synchronisation is lost. After reading by the microprocessor, ECR is put to ”0”. STLC5460 31/54 |
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