STLC60133

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ELECTRICAL CHARACTERISTICS

unless otherwise specified.) The limits listed below are guaranted in the above temperature range by (0-70°C)

specific testing at different temperature or by product characterisation.

TRANSMISSION PATH

Notes: 1. The output stage of the STLC60133 is designed for maximum load current capability. As a result, shorting the output to common

can cause the STLC60133 to source or sink 1.4A.

2. Guaranteed by product characterization.

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

SR

Slew Rate

G = 6, Vout = 2Vpp

400

V/us

GBW

Gain Bandwidth

G = 6, Vout = 2Vpp, f = 5MHz

90

140

MHz

THD

Single Ended Distortion

G = 6, f = 1MHz, Vout = 6Vpp,

Rl = 25

Ω

Rl = 100

Ω

-40

-45

-46

-51

dBc

DTHD

G = 6, f = 1MHz, Vout = 12Vpp,

Rl = 25

Ω

Rl = 100

Ω

-50

-55

dBc

IMD

Single Ended IMD

G = 6, Vout = 1.5Vp each tone,

f = 500KHz,

∆f = 10KHz

Rl = 25

Ω

Rl = 100

Ω

-65

-70

-76

-81

dBc

DIMD

G = 6, Vout = 3Vp each tone,

f = 500KHz,

∆f = 10KHz

Rl = 25

Ω

Rl = 100

Ω

-77

-82

dBc

IB

Input Biasing

5

µA

VN

Voltage Noise (RTI)

f = 30KHz

4

10

nV/

IOV

Input Offset Voltage

6mV

ICMR

Input Common Mode Voltage

Range

f = 1 MHz

-1

+1

V

CMRR

Common Mode Rejection Ratio

f = 1 MHz, Vin = 100mV

40

dB

OVS

Output Voltage Swing

Single ended, Rl = 100

Ω,

G = 6

-5

+5

V

LOC

Linear Output Current

Single ended, Rl = 10

Ω,

G = 6

300

420

mA

SCC

Single ended,

1000

1400

mA

QC

Quiescent Current

PWDN1, PWDN0 = 1,1

PWDN1, PWDN0 = 1,0

PWDN1, PWDN0 = 0,1

PWDN1, PWDN0 = 0,0

10

7

5

3.5

13.7

9

6.5

4.5

mA/Amp

SC

Shutdown Current

250

µA out of Bias pin

1.5

2.0

mA/Amp

PSRR

Power Supply Rejection ratio

f = 500kHz, V = 100mV

30

40

dB

BIASV

Bias Pin Voltage

4

4.5

V

DCG

DC Gain

80

dB

Hz