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September 2004

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5V TOLERANT INPUTS AND OUTPUTS

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HIGH SPEED:

s

POWER DOWN PROTECTION ON INPUTS

AND OUTPUTS

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SYMMETRICAL OUTPUT IMPEDANCE:

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PCI BUS LEVELS GUARANTEED AT 24 mA

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BALANCED PROPAGATION DELAYS:

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OPERATING VOLTAGE RANGE:

Retention)

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PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 573

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LATCH-UP PERFORMANCE EXCEEDS

500mA (JESD 17)

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ESD PERFORMANCE:

HBM > 2000V (MIL STD 883 method 3015);

MM > 200V

DESCRIPTION

The 74LCX573 is a low voltage CMOS OCTAL

D-TYPE

LATCH

with

3

STATE

OUTPUT

NON-INVERTING

fabricated

with

sub-micron

technology. It is ideal for low power and high

speed 3.3V applications; it can be interfaced to 5V

signal environment for both inputs and outputs.

These 8 bit D-Type latch are controlled by a latch

enable input (LE) and an output enable input (OE).

While the LE inputs is held at a high level, the Q

outputs will follow the data input. When the LE is

taken low, the Q outputs will be latched at the logic

level of D input data. While the (OE) input is low,

the 8 outputs will be in a normal logic state (high or

low logic level) and while (OE) is in high level, the

outputs will be in a high impedance state.

It has same speed performance at 3.3V than 5V

AC/ACT family, combined with a lower power

consumption.

All

inputs

and

outputs

are

equipped

with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

74LCX573

OCTAL D-TYPE LATCH NON-INVERTING (3-STATE)

WITH 5V TOLERANT INPUTS AND OUTPUTS

Figure 1: Pin Connection And IEC Logic Symbols

Table 1: Order Codes

PACKAGE

T & R

SOP

74LCX573MTR

TSSOP

74LCX573TTR

TSSOP

SOP

Rev. 5