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STLC60134 数据表(PDF) 3 Page - STMicroelectronics

部件名 STLC60134
功能描述  TOSCA INTEGRATED ADSL CMOS ANALOG FRONT-END CIRCUIT
PDF  22 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STLC60134 数据表(HTML) 3 Page - STMicroelectronics

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Maximum / minimum signal levels
The following table gives the transmitted and re-
ceived signal levels for both ATU-R and ATU-C
sides. All the levels are referred to the line volt-
ages (i.e. after hybrid and transformers in TX di-
rection, before hybrid and transformer in RX di-
rection).
Note that signal amplitudes shown below are for
illustration purpose and depending on the trans-
mit power and line impedance signal amplitudes
can differ from these values.
The reference line impedance for all power calcu-
lations is 100
Ω.
PACKAGE
The STLC60134S is packaged in a 64-pin TQFP
package (body size 10x10mm, pitch 0.5mm).
Table 1. Target Signal Levels (on the line).
Parameter
ATU - C
ATU - R
RX
TX
RX
TX
Max level
839 mVpdif
15.8 Vpdif
3.95 Vpdif
3.4 Vpdif
Max RMS level
168 mVrms
3.16 Vrms
791 mVrms
671 mVrms
Min level
54 mVpdif
3.95 Vpdif
42 mVpdif
839 mVpdif
Min RMS level
11 mVrms
791 mVrms
8 mVrms
168 mVrms
Table 2. Total Signal Level (on the line).
Parameter
ATU - C
ATU - R
RX
TX
RX
TX
Max level for receiver
4 Vpdif (Long line)
4.2 Vpdif (Short line)
1
2
3
5
6
4
7
8
9
10
27
11
28 29 30 31 32
59 58 57 56
54
55
53 52 51 50 49
43
42
41
39
38
40
48
47
46
44
45
NU0
NU1
NU2
TX0
TX1
NU3
CLWD
CLNIB
CLKM
CTRLIN
DVSS1
GP2
AVDD6
AVDD5
RES
AGND
RES
RXIP0
RXIN0
GC1
VCOC
GC0
D98TL355mod
22 23 24 25 26
60
61
62
63
64
17 18 19 20 21
37
36
34
33
35
RES
RES
AVSS4
GP1
AVSS5
12
13
14
15
16
DVDD1
RX0
RX1
RX3
RX2
Figure 2. Pin Connection
STLC60134S
3/22



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