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July 2004

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5V TOLERANT INPUTS

s

s

POWER DOWN PROTECTION ON INPUTS

AND OUTPUTS

s

SYMMETRICAL OUTPUT IMPEDANCE:

s

PCI BUS LEVELS GUARANTEED AT 24 mA

s

BALANCED PROPAGATION DELAYS:

s

OPERATING VOLTAGE RANGE:

Retention)

s

PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 125

s

LATCH-UP PERFORMANCE EXCEEDS

500mA (JESD 17)

s

ESD PERFORMANCE:

HBM > 2000V (MIL STD 883 method 3015);

MM > 200V

DESCRIPTION

The 74LVC125A is a low voltage CMOS QUAD

BUS BUFFER fabricated with sub-micron silicon

operations

and

low

power

and

low

noise

applications.

It can be interfaced to 5V signal environment for

inputs in mixed 3.3/5V system.

These devices require the same 3-STATE control

input G to be taken high to make the output go in

to the high impedance state.

It has more speed performance at 3.3V than 5V

AC/ACT family, combined with a lower power

consumption.

All

inputs

and

outputs

are

equipped

with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

74LVC125A

LOW VOLTAGE CMOS QUAD BUS BUFFERS (3-STATE)

HIGH PERFORMANCE

Figure 1: Pin Connection And IEC Logic Symbols

Table 1: Order Codes

PACKAGE

T & R

SOP

74LVC125AMTR

TSSOP

74LVC125ATTR

TSSOP

SOP

Rev. 8