1/14

July 2004

s

5V TOLERANT INPUTS

s

s

POWER DOWN PROTECTION ON INPUTS

AND OUTPUTS

s

SYMMETRICAL OUTPUT IMPEDANCE:

s

PCI BUS LEVELS GUARANTEED AT 24 mA

s

BALANCED PROPAGATION DELAYS:

s

OPERATING VOLTAGE RANGE:

Retention)

s

PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 374

s

LATCH-UP PERFORMANCE EXCEEDS

500mA (JESD 17)

s

ESD PERFORMANCE:

HBM > 2000V (MIL STD 883 method 3015);

MM > 200V

DESCRIPTION

The 74LVC374A is an advanced high-speed

CMOS OCTAL D-TYPE FLIP FLOP with 3 STATE

OUTPUTS NON INVERTING fabricated with

sub-micron silicon gate and double-layer metal

These 8 bit D-Type latch are controlled by a clock

input (CK) and an output enable input (OE).

On the positive transition of the clock, the Q

outputs will be set to the logic state that were

setup at the D inputs.

While the (OE) input is low, the 8 outputs will be in

a normal logic state (high or low logic level) and

while high level the outputs will be in a high

impedance state.

The Output control does not affect the internal

operation of flip flops; that is, the old data can be

retained or the new data can be entered even

while the outputs are off. Power down protection is

provided on all inputs and 0 to 7V can be accepted

on inputs with no regard to the supply voltage.

This device can be used to interface 5V to 3V.

All

inputs

and

outputs

are

equipped

with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

74LVC374A

OCTAL D-TYPE FLIP-FLOP

HIGH PERFORMANCE

Figure 1: Pin Connection And IEC Logic Symbols

Table 1: Order Codes

PACKAGE

T & R

SOP

74LVC374AMTR

TSSOP

74LVC374ATTR

TSSOP

SOP

Rev. 2