STMEC001

Logic characteristics

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6

Logic characteristics

Table 10.

Logic states

Logic transition

Condition

Min

Typ

Max

Unit

Logic input voltage

High level

2.0

V

Low level

0.8

PERST# assertion threshold of output

voltage

3.3 V output falling

2.7

3.0

V

AUX output falling

2.7

3.0

1.5 V output falling

1.2

1.35

PERST# assertion delay from output

voltage invalid

Output falling below threshold

500

ns

PERST# de-assertion from output

voltage valid

Output rising above threshold

4

10

20

ms

PERST# assertion delay from SYSRST# STSRST asserted or de-asserted

500

ns

RCLKEN assertion delay from output

voltage valid

Output rising above threshold

100

μs

OC# output low voltage

0.4

V

OC# leakage current

1

μA

OC# deglitch

Falling into or out of an over-current

condition

620

μs

Table 11.

ESD protections

Pin

Condition

ESD tolerance

Unit

Versus GND & supply

6

kV

All other pins (except RCLKEN)

Versus GND & supply

2

RCLKEN

Versus GND

2

RCLKEN

Versus supply

1