Key matrix and key-input data storage ram

STLED316S

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Key matrix and key-input data storage ram

During the key scan cycle all the grids are turned off. The first segments turn on is 64 µs.

The key1 and key2 signals will be sampled after 60 µs. The two signals latch into the

internal key buffer. The same applies for other segments.

This key buffer compares the data with the previous key status. If any changes are seen in

the buffer values, then the IRQ_N is asserted. The IRQ_N signal is active low (level). This

IRQ_N signal will be cleared at the end of reading the key buffer (end of byte transfer). The

key buffer must be completely read before the IRQ_N is cleared.

The key matrix is of 8 x 2 configuration, as shown below:

Figure 4.

Key matrix

The data of each key are stored as illustrated below, and are read by the appropriate read

command, starting from the least significant bit.

The initial key buffer value is “00”. During operation, the buffer values will change depending

upon the values of the key-press.

KEY1

KEY1

KEY1

KEY1

KEY1

KEY1

KEY1

KEY1

SEG1/KS1

SEG2/KS2

SEG3/KS3

SEG4/KS4

SEG5/KS5

SEG6/KS6

SEG7/KS7

SEG8/KS8

LSB

MSB

KEY2

KEY2

KEY2

KEY2

KEY2

KEY2

KEY2

KEY2

SEG1/KS1

SEG2/KS2

SEG3/KS3

SEG4/KS4

SEG5/KS5

SEG6/KS6

SEG7/KS7

SEG8/KS8

LSB

MSB