STM1403ATMQ6F datasheet(14/34 Pages) STMICROELECTRONICS

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Operation

STM1403

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Operation

3.1

Reset input

The STM1403 security supervisor asserts a reset signal to the MCU whenever VCC goes

below the reset threshold (VRST), or when the push-button reset input (MR) is taken low.

RST is guaranteed to be a logic low for 0V < VCC < VRST if VBAT is greater than 1V. Without

a backup battery, RST is guaranteed valid down to VCC =1V.

During power-up, once VCC exceeds the reset threshold an internal timer keeps RST low for

the reset time-out period, trec. After this interval RST returns high.

If VCC drops below the reset threshold, RST goes low. Each time RST is asserted, it stays

low for at least the reset time-out period (trec). Any time VCC goes below the reset threshold

the internal timer clears. The reset timer starts when VCC returns above the reset threshold.

3.2

Push-button reset input

A logic low on MR asserts reset. Reset remains asserted while MR is low, and for trec (see

Figure 25 on page 24) after it returns high. The MR input has an internal 40 k

Ω pull-up

resistor, allowing it to be left open if not used. This input can be driven with TTL/CMOS-logic

levels or with open-drain/collector outputs. Connect a normally open momentary switch from

MR to ground to create a manual reset function; external debounce circuitry is not required.

If MR is driven from long cables or the device is used in a noisy environment, connect a

0.1 µF capacitor from MR to VSS to provide additional noise immunity. MR may float, or be

tied to VCC when not used.

3.3

Backup battery switchover

In the event of a power failure, it may be necessary to preserve the contents of external

SRAM through VOUT. With a backup battery installed with voltage VBAT, the devices

automatically switch the SRAM to the backup supply when VCC falls.

Note:

If backup battery is not used, connect both VBAT and VOUT to VCC.

This family of security supervisors does not always connect VBAT to VOUT when VBAT is

greater than VCC. VBAT connects to VOUT (through a 100 Ω switch) when VCC is below VSW

(~2.4 V) or VBAT (whichever is lower). This is done to allow the backup battery (e.g., a 3.6 V

battery) to have a higher voltage than VCC.

Assuming that VBAT > 2.0 V, switchover at VSO ensures that battery backup mode is entered

before VOUT gets too close to the 2.0 V minimum required to reliably retain data in most

external SRAMs. When VCC recovers, hysteresis is used to avoid oscillation around the VSO

point. VOUT is connected to VCC through a 3 Ω PMOS power switch.

Note:

The backup battery may be removed while VCC is valid, assuming VBAT is adequately

decoupled (0.1 µF typ), without danger of triggering a reset.

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