Operation

STM1810/1811/1812/1813/1815/1816/1817/1818

10/25

threshold and lasts 20 µs or less will not cause a reset pulse. A 0.1 µF bypass capacitor

2.5

circuit. In most systems this is not a problem, as most MCUs do not operate below 1 V.

However, in applications where RST output must be valid down to 0 V, a pull-down resistor

may be added to hold the RST output low (see Figure 12). This resistor must be large

enough to not load the RST output, and still be small enough to pull the output to ground. A

100 k

Ω resistor is recommended.

Note:

The same situation applies for the active-high RST of the STM1810/1812. A 100 k

Figure 8.

Reset timing diagram

1.

RST for STM1812 and STM1817.

Figure 9.

Push-button manual reset with MR detect (STM1813/1818)

AI09653

RST

RST

(1)

VCC

VRST

VCC (min)

trec

trec

AI09654

STM1813

STM1818

RST

Push-button RESET

Micro RESET

5.5 k

Ω

Reset

Monitor