STTS424E02BDA3F datasheet(33/51 Pages) STMICROELECTRONICS

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STTS424E02

SPD EEPROM operation

33/51

Figure 13.

Write cycle polling flowchart using ACK

5.5.3

Minimizing system delays by polling on ACK

During the internal Write cycle, the device disconnects itself from the bus, and writes a copy

of the data from its internal latches to the memory cells. The maximum Write time (tw) is

shown inTable 2: AC SMBus and I2C compatibility timings , but the typical time is shorter. To

make use of this, a polling sequence can be used by the bus master.

The sequence, as shown in Figure 13, is:

●

Initial condition: a Write cycle is in progress.

●

Step 1: the bus master issues a Start condition followed by a Device Select Code (the

first byte of the new instruction).

●

Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and

the bus master goes back to Step 1. If the device has terminated the internal Write

cycle, it responds with an Ack, indicating that the device is ready to receive the second

part of the instruction (the first byte of this instruction having been sent during Step 1).

WRITE Cycle

in Progress

AI01847C

Operation is

Addressing the

Memory

START Condition

DEVICE SELECT

with RW = 0

ACK

Returned

YES

ReSTART

STOP

DATA for the

WRITE Operation

DEVICE SELECT

with RW = 1

Send Address

and Receive ACK

First byte of instruction

with RW = 0 already

decoded by the device

YES

START

Condition

Continue the

WRITE Operation

Continue the

Random READ Operation

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