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74VHC74 数据表(PDF) 5 Page - STMicroelectronics

部件名 74VHC74
功能描述  DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR
PDF  14 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

74VHC74 数据表(HTML) 5 Page - STMicroelectronics

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Table 7: AC Electrical Characteristics (Input tr = tf = 3ns)
(*) Voltage range is 3.3V
± 0.3V
(**) Voltage range is 5.0V
± 0.5V
Table 8: Capacitive Characteristics
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/2 (per
flip-flop)
Symbol
Parameter
Test Condition
Value
Unit
VCC
(V)
CL
(pF)
TA = 25°C
-40 to 85°C
-55 to 125°C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
tPLH
tPHL
Propagation Delay
Time CK to Q or Q
3.3(*)
15
6.7
11.9
1.0
14.0
1.0
14.0
ns
3.3(*)
50
9.2
15.4
1.0
17.5
1.0
17.5
5.0(**)
15
4.6
7.3
1.0
8.5
1.0
8.5
5.0(**)
50
6.1
9.3
1.0
10.5
1.0
10.5
tPLH
tPHL
Propagation Delay
Time PR or CLR to
Q or Q
3.3(*)
15
7.6
12.3
1.0
14.5
1.0
14.5
ns
3.3(*)
50
10.1
15.8
1.0
18.0
1.0
18.0
5.0(**)
15
4.8
7.7
1.0
9.0
1.0
9.0
5.0(**)
50
6.3
9.7
1.0
11.0
1.0
11.0
tW
CK Pulse Width
HIGH or LOW
3.3(*)
6.0
7.0
7.0
ns
5.0(**)
5.0
5.0
5.0
tW
PR or CLR Pulse
Width LOW
3.3(*)
6.0
7.0
7.0
ns
5.0(**)
5.0
5.0
5.0
ts
Setup Time D to CK
HIGH or LOW
3.3(*)
6.0
7.0
7.0
ns
5.0(**)
5.0
5.0
5.0
th
Hold Time D to CK
HIGH or LOW
3.3(*)
0.5
0.5
0.5
ns
5.0(**)
0.5
0.5
0.5
tREM
Removal Time
PR or CLR to CK
3.3(*)
5.0
5.0
5.0
ns
5.0(**)
3.0
3.0
3.0
fMAX
Maximum Clock
Frequency
3.3(*)
15
80
125
70
70
MHz
3.3(*)
50
50
75
45
45
5.0(**)
15
130
170
110
110
5.0(**)
50
90
115
75
75
Symbol
Parameter
Test Condition
Value
Unit
VCC
(V)
TA = 25°C
-40 to 85°C
-55 to 125°C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
CIN
Input Capacitance
5.0
7
10
10
10
pF
CPD
Power Dissipation
Capacitance
(note 1)
5.0
fIN = 10MHz
25
pF



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