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ESDA17SC6 数据表(PDF) 6 Page - STMicroelectronics

部件名 ESDA17SC6
功能描述  Quad Transil array for ESD protection
PDF  11 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ESDA17SC6 数据表(HTML) 6 Page - STMicroelectronics

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Technical information
ESDAxxSCx
6/11
3
Technical information
3.1
ESD protection
The ESDA19SC6 is particularly optimized to perform ESD protection. ESD protection is
achieved by clamping the unwanted overvoltage. The clamping voltage is given by the
following formula :
VCL = VBR + Rd . IPP
As shown in Figure 11., the ESD strikes are clamped by the transient voltage suppressor.
Figure 11.
ESD clamping behavior (example)
To have a good approximation of the remaining voltages at both VI/O side, we provide the
typical dynamical resistance value Rd. By taking into account the following hypothesis :
R
g > Rd and Rload > Rd
we have:
The results of the calculation done for Vg = 8 kV, Rg = 330
Ω (IEC61000-4-2 standard),
VBR = 19 V (typ.) and Rd = 0.80
Ω (typ.) give:
Vouput = 38.4 V
This confirms the very low remaining voltage across the device to be protected. It is also
important to note that in this approximation the parasitic inductance effect was not taken into
account. This could be a few tenths of volts during a few nanoseconds at the output side.
ESD Surge
Voutput
Rload
Rg
Rd
VBR
Vg
Device
to be
protected
ESDA19SC6
V
output
V
BR
R
d
+
V
g
R
g
-------
×
=



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