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September 2001

s

MEDIUM SPEED OPERATION 10 MHz (Typ.)

s

FULLY STATIC OPERATION

s

STANDARDIZED SYMMETRICAL OUTPUT

CHARACTERISTICS

s

QUIESCENT CURRENT SPECIFIED UP TO

20V

s

5V, 10V AND 15V PARAMETRIC RATINGS

s

INPUT LEAKAGE CURRENT

s

100% TESTED FOR QUIESCENT CURRENT

s

MEETS ALL REQUIREMENTS OF JEDEC

JESD13B " STANDARD SPECIFICATIONS

FOR DESCRIPTION OF B SERIES CMOS

DEVICES"

DESCRIPTION

The HCF4018B is a monolithic integrated circuit

fabricated

in

Metal

Oxide

Semiconductor

technology available in DIP and SOP packages.

The HCF4018B consist of 5 Johnson counter

stages, buffered Q outputs from each stage, and

counter preset control gating. CLOCK, RESET,

DATA, PRESET ENABLE, and 5 individual JAM

inputs are provided. Divide by 10, 8, 6, 4 or 2

counter configuration can be implemented by

feeding the Q5, Q4, Q3, Q2, Q1

signals,

respectively, back to the data input.

Divide-by-9, 7, 5, or 3 counter configurations can

be implemented by the use of a HCF4011B gate

package to properly gate the feedback connection

to the DATA input. Divide-by-functions greater

than 10 can be achieved by use of multiple

HCF4018B units. The counter is advanced one

count at the positive clock signalstransition.

Schmitt trigger action on the clock line permits

unlimited clock rise and fall times. A high RESET

signal clears the counter to an all-zero condition. A

high

PRESENT-ENABLE

signal

allows

information on the JAM inputs to preset the

counter.

Anti-lock gating is provided to assure the proper

counting sequence.

HCF4018B

PRESETTABLE DIVIDE-BY-N COUNTER

PIN CONNECTION

ORDER CODES

PACKAGE

TUBE

T & R

DIP

HCF4018BEY

SOP

HCF4018BM1

HCF4018M013TR

DIP

SOP