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ESDA6V1BC6 数据表(PDF) 3 Page - STMicroelectronics |
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ESDA6V1BC6 数据表(HTML) 3 Page - STMicroelectronics |
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3 / 6 page ![]() ESDA6V1BC6 3/6 ® 1. ESD protection by ESDA6V1-4BC6 With the focus of lowering the operation levels, the problem of malfunction caused by the environment is critical. Electrostatic discharge (ESD) is a major cause of failure in electronic system. Transient Voltage Suppressors are an ideal choice for ESD protection and have proven capable in sup- pressing ESD events. They are capable of clamping the incoming transient to a low enough level such that damage to the protected semiconductor is prevented. Surface mount TVS arrays offer the best choice for minimal lead inductance. They serve as parallel protection elements, connected between the signal line to ground. As the transient rises above the operating voltage of the device, the TVS array becomes a low impedance path diverting the transient current to ground. Figure 4: Clamping voltage versus peak pulse current (typical values, rectangular waveform) Figure 5: Junction capacitance versus line voltage applied (typical values Figure 6: Relative variation of leakage current versus junction temperature (typical values) I (A) PP 0 5 10 15 20 25 30 35 40 0.1 1.0 10.0 20.0 V (V) CL t = 2.5µs T p j initial = 25°C C(pF) 0 1 2 3 45 67 8 10 11 12 13 14 15 16 17 18 19 20 21 22 V (V) R F = 1MHz V = 30mV T OSC j = 25°C I [T ] / I [T =25°C] Rj Rj 25 50 75 100 125 150 1 10 100 500 T (°C) j |
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