M54HC597

2/14

Figure 1: IEC Logic Symbols

Figure 2: Input And Output Equivalent Circuit

Table 1: Pin Description

Table 2: Truth Table

X : Don’t Care

PIN N°

SYMBOL

NAME AND FUNCTION

9

QH’

Serial Data Outputs

10

SCLR

Asynchronous Reset

Input (Active LOW)

11

SCK

Shift Clock Input (LOW to

HIGH Edge-triggered)

12

RCK

Storage Clock Input (LOW

to HIGH Edge-triggered)

13

SLOAD

Parallel Data Input (Active

Low)

10

SI

Serial Data Input

15, 1,2,3, 4,

5, 6, 7

A to H

Parallel Data Inputs

8

GND

Ground (0V)

16

Positive Supply Voltage

INPUTS

OUTPUT

SI

SCK

SCLR

SLOAD

RCK

X

X

L

H

X

S.R. IS CLEARED TO "L"

X

X

H

L

X

INPUT REGISTER DATA IS STORED INTO S.R.

L

HHX

FIRST STAGE OF S.R. BECOMES "L" OTHER STAGES

STORE THE DATA OF PREVIOUS STAGE, RESPECTIVELY

H

HHX

FIRST STAGE OF S.R. BECOMES "H" OTHER STAGES

STORE THE DATA OF PREVIOUS STAGE, RESPECTIVELY

X

H

H

X

STATEOF S.R. ISNOT CHANGED

XXX

X

INPUT DATA ON A ~ H LINE IS STORED INTO INPUT REG-

ISTER

X

X

X

X

STORAGE REGISTER STATE IS NOT CHANGED