HCF40103B

2/14

inputs are high at the time of zero count, the

counters will jump to the maximum count, giving a

counting sequence of 256 clock pulses long.

HCF40103B may be cascaded using the CI/CE

input

and

the

CO/ZD

output,

in

either

a

synchronous or ripple mode.

IINPUT EQUIVALENT CIRCUIT

PIN DESCRIPTION

FUNCTIONAL DIAGRAM

TRUTH TABLES

X : Don’t Care

Clock connected to Clock input

Synchronous Operation : changes occur on negative to positive clock transitions.

PIN No

SYMBOL

NAME AND FUNCTION

1

CLOCK

Clock Input (LOW to

HIGH edge triggered)

2

CLEAR

Asynchronous Master

Reset Input (Active Low)

3

CI/CE

Terminal Enable Input

4, 5, 6, 7, 10,

11, 12, 13

J0 to J7

Jam Inputs

9APE

Asynchronous Preset

Enable Inputs(Active Low)

14

CO/ZD

Terminal Count Output

(Active Low)

15

SPE

Synchronous Preset

Enable Input (Active Low)

8

Negative Supply Voltage

16

Positive Supply Voltage

CONTROL INPUTS

PRESET MODE

ACTION

CLR

APE

SPE

CI/CE

HH

HH

Synchronous

Inhibit Counter

H

H

H

L

Count Down

H

H

L

X

Preset on Next Positive Clock Transition

HL

X

X

Asynchronous

Preset Asynchronously

L

X

X

X

Clear to Maximum Count