KBMF

3/8

2. ESD PROTECTION

The KBMFxxSC6 is particularly optimized to perform ESD protection. ESD protection is based on the use

of device which clamps at:

This protection function is splitted in 2 stages. As shown in figure 4, the ESD strikes are clamped by the

first stage S1 and then its remaining overvoltage is applied to the second stage through the resistor R.

This confirms the very low remaining voltage across the device to be protected. It is also important to note

that in this approximation the parasitic inductance effect was not taken into account. This could be few

tenths of volts during few ns at the input side. This parasitic effect is not present at the output side due the

The measurements done here after show very clearly (figure 6) the high efficiency of the ESD protection :

- no influence of the parasitic inductances on output stage

Figure 4: ESD clamping behavior

ESD Surge

Vinput

Voutput

Rload

Rg

Rs

S1

Rd

V

BR

V

BR

V

PP

Device

to be

protected

KBMFxxSC6

Rd

S2

V

input

=

R

g

V

BR

R

d

V

g

⋅

+

⋅

R

g

------------------------------------------------------

V

output

=

R

s

V

BR

R

d

V

input

⋅

+

⋅

R

t

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