L4972A

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Table 2. Pin Description

Figure 3. Pin Connection (Top view)

N°

Pin

Function

1

BOOTSTRAP

properly the internal D-MOS transistor.

2

RESET DELAY

signal delay time.

3

RESET OUT

Open Collector Reset/power Failand the output voltages are safe. Signal Output.

This output is high when the supply

4

RESET INPUT

Input of Power Fail Circuit. The threshold is 5.1V. It may be connected via a divider

to the input for power fail function. It must be connected to the pin 14 an external

30K

Ω resistor when power fail signal not required.

5, 6 15,

16

GROUND

Common Ground Terminal

7

FREQUENCY

COMPENSATION

A series RC network connected between this terminal and ground determines the

regulation loop gain characteristics.

8

SOFT START

Soft Start Time Constant. A capacitor is connected between the sterminal and

ground to define the soft start time constant.

9

FEEDBACK INPUT

The Feedback Terminal of the Regulation Loop. The output is connected directly to

this terminal for 5.1V operation; It is connected via a divider for higher voltages.

10

SYNC INPUT

Multiple L4972A’s are synchronized by connecting pin 10 inputs together or via an

external syncr. pulse.

11

SUPPLY VOLTAGE

Unregulated Input Voltage.

12, 19

N.C.

Not Connected.

13

14

Internal Start-up Circuit to Drive the Power Stage.

17

OSCILLATOR

18

OSCILLATOR

frequency.

20

OUTPUT

Regulator Output.

1

3

2

4

5

6

7

8

9

20

19

18

17

16

14

15

13

12

DIP20

10

11

GND

FREQ. COMP.

SOFT START

SYNC INPUT

FEEDBACK IN.

N.C.

Vi

Vref

Vstart

GND

BOOTSTRAP

RESET DELAY

RESET OUT

P. FAIL INPUT

GND

GND

R OSC

C OSC

N.C.

OUTPUT