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L6725ATR 数据表(PDF) 7 Page - STMicroelectronics

部件名 L6725ATR
功能描述  Voltage mode PWM controller with bootstrap anti-discharging system
PDF  32 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

L6725ATR 数据表(HTML) 7 Page - STMicroelectronics

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L6725 - L6725A
Pin connections and functions
7/32
Pin n°
Name
Function
5OCH
A resistor connected from this pin and the high-side MOSFET(s) drain sets the peak-
current-limit. The peak current is sensed through the high-side MOSFET(s). The
internal 100
µA current generator (IOCH) sinks a current from the drain through the
external resistor (ROCH). The over-current threshold is given by the following
equation:
6
PHASE
This pin is connected to the source of the high-side MOSFET(s) and provides the
return path for the high-side driver. This pin monitors the drop across both the upper
and lower MOSFET(s) for the current limit together with OCH and OCL.
7
HGATE
This pin is connected to the high-side MOSFET(s) gate.
8BOOT
Through this pin is supplied the high-side driver. Connect a capacitor from this pin to
the PHASE pin and a diode from VCCDR to this pin (cathode versus BOOT).
9PGND
This pin has to be connected closely to the low-side MOSFET(s) source in order to
reduce the noise injection into the device.
10
LGATE
This pin is connected to the low-side MOSFET(s) gate.
11
VCCDR
5V internally regulated voltage. It is used to supply the internal drivers. Filter it to
ground with a 1uF ceramic cap.
12
VCC
Supply voltage pin. The operative supply voltage range is from 4.5V to 14V.
13
PGOOD
(L6725A)
N.C.
(L6725)
In L6725 this pin is N.C. With L6725A this pin is an open collector output and it is
pulled low if the output voltage is not
within the specified thresholds (90%-110%). If not used it may be left floating. Pull-up
this pin to VCCDR with a 10K resistor to obtain a logical signal.
14
SYNCH
(L6725A)
N.C.
(L6725)
In L6725 this pin is N.C. With L6725A it is a Master-Slave pin. Two or more devices
can be synchronized by simply
connecting the SYNCH pins together. The device operating with the highest FSW will
be the Master. The Slave devices will operate with 180° phase shift from the Master.
The best way to synchronize devices together is to set their FSW at the same value. If
it is not used the SYNCH pin can be left floating.
15
SGND
All the internal references are referred to this pin.
16
FB
This pin is connected to the error amplifier inverting input. Connect it to VOUT through
the compensation network. This pin is also used to sense the output voltage in order
to manage the over voltage protection.
Table 4.
Pin functions
DSonHS
R
OCH
R
OCH
I
PEAK
I
=



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