TDA7381

Application hints

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3

Application hints

3.1

Biasing and SVR

As shown by Figure 3, all the TDA7381’s main sections, such as Inputs, Outputs and AC-

GND (pin 16) are internally biased at half supply voltage level (Vs/2), which is derived from

the supply voltage rejection (SVR) block. In this way no current flows through the internal

feedback network.

The AC-GND is common to all the 4 amplifiers and represents the connection point of all the

inverting inputs. Both individual inputs and AC-GND are connected to Vs/2 (SVR) by means

of 100 k

Ω resistors.

To ensure proper operation and high supply voltage rejection, it is of fundamental

importance to provide a good impedance matching between INPUTS and AC-GROUND

terminations.

their tolerance should never exceed ±10 %.

Besides its contribution to the ripple rejection, the SVR capacitor governs the turn ON/OFF

time sequence and, consequently, plays an essential role in the pop optimization during

ON/OFF transients. To conveniently serve both needs, its minimum recommended value

is 10

μF.

3.2

Input stage

The TDA7381’S inputs are ground-compatible and can stand very high input signals

(± 8 Vpk) without any performances degradation. If the standard value for the input

capacitors (0.1

μF) is adopted, the low frequency cut-off will amount to 16 Hz.

3.3

Stand-by and muting

Stand-by and muting facilities are both CMOS-compatible. If unused, a straight connection

to Vs of their respective pins would be admissible.

Conventional low-power transistors can be employed to drive muting and stand-by pins in

absence of true CMOS ports or microprocessors. R-C cells have always to be used in order

to smooth down the transitions for preventing any audible transient noises. Since a DC

current of about 10

μA normally flows out of pin 22, the maximum allowable muting-series

small (about 1

μF). If R

voltage at pin 22 may rise to above the 1.5 V threshold voltage and the device will

consequently fail to turn OFF when the mute line is brought down.

About the stand-by, the time constant to be assigned in order to obtain a virtually pop-free

transition has to be slower than 2.5 V/ms.