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M48Z2M1V 数据表(PDF) 5 Page - STMicroelectronics

部件名 M48Z2M1V
功能描述  5V or 3.3V, 16 Mbit (2Mb x 8) ZEROPOWER SRAM
PDF  17 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

M48Z2M1V 数据表(HTML) 5 Page - STMicroelectronics

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M48Z2M1Y, M48Z2M1V
Figure 4. Block Diagram
OPERATION MODES
The M48Z2M1Y/V has its own Power-fail Detect
Circuit. The control circuitry constantly monitors
the single 5V supply for an out of tolerance condi-
tion. When VCC is out of tolerance, the circuit write
protects the SRAM, providing a high degree of
data security in the midst of unpredictable system
operations brought on by low VCC. As VCC falls be-
low approximately 3V, the control circuitry con-
nects the batteries which sustain data until valid
power returns.
Table 2. Operating Modes
Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.
1. See Table 10., page 13 for details.
AI02050
INTERNAL
BATTERIES
E
VCC
VSS
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
2048K x 8
SRAM ARRAY
A0-A20
DQ0-DQ7
W
G
POWER
E
Mode
VCC
E
G
W
DQ0-DQ7
Power
Deselect
3.0 to 3.6V
or
4.5 to 5.5V
VIH
X
X
High Z
Standby
WRITE
VIL
X
VIL
DIN
Active
READ
VIL
VIL
VIH
DOUT
Active
READ
VIL
VIH
VIH
High Z
Active
Deselect
VSO to VPFD (min)
(1)
X
X
X
High Z
CMOS Standby
Deselect
≤ VSO(1)
X
X
X
High Z
Battery Back-up Mode



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